Counter based on phase-lock loop pulse interpolation technology and realization method

A counter and phase-locked loop technology, applied in the field of counters based on phase-locked loop pulse interpolation technology, can solve the problems of large calibration equipment, reduce the size of the calibration equipment, shorten the calibration time, etc., to shorten the calibration time, reliable performance, low cost effect

Inactive Publication Date: 2013-08-14
UNIV OF SHANGHAI FOR SCI & TECH
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Problems solved by technology

[0003] The present invention aims at the problems that the calibration time is long, the calibration equipment is bulky, and the calibration accuracy is affected by the frequency and duty cycle of the input pulse signal in the calibration process of the existing flow calibration device. The counte

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  • Counter based on phase-lock loop pulse interpolation technology and realization method
  • Counter based on phase-lock loop pulse interpolation technology and realization method
  • Counter based on phase-lock loop pulse interpolation technology and realization method

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Embodiment Construction

[0023] Such as figure 1 It is the schematic diagram of the phase-locked loop pulse interpolation method. The pulse signal sent by the flowmeter is input to the phase comparator as signal 1, and the output signal of the phase comparator enters the voltage controlled oscillator (hereinafter referred to as VCO) after being filtered by a filter. The oscillator generates a high frequency pulse signal proportional to the input voltage. This frequency should be chosen higher than the frequency of the flowmeter.

[0024] The output signal of the VCO is processed by the frequency divider, and then fed back to the phase comparator as the input signal 2. Divisor of pulse signal with increased frequency N attenuation. The output voltage of a phase comparator is proportional to the phase difference or frequency difference between the two input signals. Therefore, the output frequency of the VCO is continuously servo controlled, ensuring that the phase or frequency between the two inpu...

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Abstract

The invention relates to a counter based on a phase-lock loop pulse interpolation technology and a realization method. A door control signal is inputted to an input/output (I/O) pin of a FPGA (field programmable gate array) circuit after being processed by a processing circuit, and a pulse signal of a detected flow meter is inputted to another I/O pin of the FPGA circuit after being processed by the processing circuit. After the phase-lock loop pulse interpolation through the FPGA circuit, the pulse signal of the flow meter is outputted to a liquid crystal display; and meanwhile, the pulse signal is outputted through an RS-232 serial communication interface. Within dozens of seconds or a shorter calibration time, and when the pulse frequency of the flow meter is dozens or smaller, the 0.01 percent pulse counting precision of the detected flow meter still can be satisfied, and the flow meter with large flow rate can be calibrated on a calibration device with a small flow rate range. By adopting the phase-lock loop pulse interpolation technology, the limit of the dual-timing method and the quadrate-timing method requiring the pulse frequency and the uniform duty ratio can be broken through.

Description

technical field [0001] The invention relates to a counter, in particular to a counter based on the phase-locked loop pulse interpolation technology and its realization method. Background technique [0002] Phase-locked loop pulse interpolation technology is mainly used in the calibration process of flowmeters with pulse output. When the volumetric method (or mass method) is used to calibrate the flowmeter, within a certain period of time, the volume of fluid flowing through the flowmeter to be calibrated can be converted from the number of pulses collected. Traditional counters can only calculate the fluid flow represented by the complete pulse signal, but cannot calculate the fluid flow represented by the incomplete pulse, thus causing measurement errors. Gathering more pulses can reduce metering errors. To ensure calibration accuracy, there is a limit on the minimum number of pulses that need to be collected during calibration. However, the number of pulses per unit vol...

Claims

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Application Information

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IPC IPC(8): H03K21/00G01F25/00H03L7/085
Inventor 沈昱明周莹莹
Owner UNIV OF SHANGHAI FOR SCI & TECH
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