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Threshold logic type carry look ahead adder formed by SET/MOS mixing circuit

A hybrid circuit and carry-ahead technology, applied in the field of microelectronics, can solve problems such as inapplicability, and achieve the effects of simplifying structure, reducing area consumption, and reducing circuit power consumption

Active Publication Date: 2013-09-04
FUZHOU UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, as CMOS technology enters the nanometer field, when the feature size of the device is close to the physical limit, the traditional method of reducing the device size to achieve low power consumption and area reduction is gradually inapplicable.

Method used

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  • Threshold logic type carry look ahead adder formed by SET/MOS mixing circuit
  • Threshold logic type carry look ahead adder formed by SET/MOS mixing circuit
  • Threshold logic type carry look ahead adder formed by SET/MOS mixing circuit

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Embodiment Construction

[0033] The present invention will be further described below in conjunction with the accompanying drawings and embodiments.

[0034]The threshold logic type look-ahead adder composed of the SET / MOS hybrid circuit proposed by the present invention adopts a design method in which a single electron transistor (Single electron transistor, SET) and a MOS transistor are mixed. Single-electron transistors have obvious advantages over traditional microelectronic devices in terms of power consumption and working speed, and are typical representatives of the new generation of nanoelectronic devices. The single-electron transistor is compatible with the CMOS silicon process, and the SET / MOS hybrid circuit has the superior performance of SET and MOS transistors, showing extremely low power consumption, ultra-small device size, strong driving capability and large output swing It is expected to be widely used in multi-valued logic circuits, analog-to-digital / digital-to-analog converter circ...

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Abstract

The invention relates to a carry look ahead adder based on threshold logic and achieved by utilizing coulomb blockade oscillation effects and multi-gate input characteristics of a single electron transistor and metal oxide semiconductor (MOS) transistor mixing structure. Due to the good logic function of threshold logic, a circuit is only formed by 10 threshold logic gates, and the whole circuit only consumes 30 components. Compared with a traditional complementary metal oxide semiconductor (CMOS) carry look ahead adder, the threshold logic type carry look ahead adder enables circuit structure to be greatly simplified, transistor number is remarkably reduced, and power consumption is further reduced. The threshold logic type carry look ahead adder can be hopefully applied to the fields of microprocessors, digital signal processors and the like, is favorable for further reducing circuit power consumption, saves chip area and improves circuit integration level.

Description

technical field [0001] The invention relates to the technical field of microelectronics, in particular to a threshold logic type look-ahead carry adder composed of a SET / MOS hybrid circuit. Background technique [0002] The adder is an important part of the microprocessor and digital signal processor. It is mainly located on its critical path and directly affects the speed of the processor. Addition is the most important and basic operation, and all other operations (subtraction, multiplication, and division) can ultimately be attributed to addition. In addition, there is a carry, so that the result of a certain bit is obtained with respect to all bits below it. This greatly affects the operation speed of the adder. In order to reduce the time spent on carry transmission and increase the calculation speed, various types of adders have emerged. [0003] In recent years, with the development of microelectronics technology, the word length of processors and computers has dou...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F7/50
Inventor 魏榕山陈锦锋于志敏何明华
Owner FUZHOU UNIV
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