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Manufacturing method for separated grid type flash memory embedded into logical circuit

A manufacturing method and a technology of separating gates, which are applied in circuits, semiconductor/solid-state device manufacturing, electrical components, etc., can solve problems such as memory operating speed signal transmission bandwidth limitations, and achieve the effect of simplifying the manufacturing process

Active Publication Date: 2015-06-03
SEMICON MFG INT (SHANGHAI) CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

If the split-gate flash memory, high-voltage circuit, and logic circuit are all built on a separate integrated chip, the operating speed of the entire memory will be limited by the signal transmission bandwidth between the flash memory and peripheral circuits

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  • Manufacturing method for separated grid type flash memory embedded into logical circuit
  • Manufacturing method for separated grid type flash memory embedded into logical circuit
  • Manufacturing method for separated grid type flash memory embedded into logical circuit

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Embodiment Construction

[0034] The technical solution of the present invention will be described clearly and completely through specific embodiments below in conjunction with the accompanying drawings. Apparently, the described embodiments are only a part of the possible implementation modes of the present invention, not all of them. According to these embodiments, all other implementation manners that can be obtained by those skilled in the art without creative efforts belong to the protection scope of the present invention.

[0035] Figure 7 It is the manufacturing flowchart of the memory in the embodiment of the manufacturing method of the separated gate type flash memory embedded in the logic circuit of the present invention, Figure 8 to Figure 19 is in Figure 7 Schematic diagram of the structure of the split-gate flash memory embedded with logic circuits during the fabrication process shown. The following will Figure 8 to Figure 19 and Figure 7 Together, the preparation method of the pr...

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Abstract

The invention provides a manufacturing method for a separated grid type flash memory embedded into a logical circuit. According to the method, the separated grid type flash memory can be embedded into a peripheral circuit of a high-voltage circuit and the logical circuit, and the separated grid type flash memory, the high-voltage circuit and the logical circuit can be manufactured on a chip at the same time. After a stacking structure, comprising a floating gate oxide layer, a floating gate, a gate medium layer, a control gate and a hard mask layer, of the memory is formed, the thickness of a memory word line gate and the thickness of an erasing gate can be defined only through two-time polycrystalline silicon layer deposition and one-time photoetching glue line imaging treatment, and compared with three-time polycrystalline silicon layer deposition and two-time photoetching glue line imaging treatment in the prior art, the method greatly simplifies a manufacturing process. In addition, a gate medium layer of a high-voltage transistor is formed before the stacking structure of the memory is formed, and therefore the high-quality gate medium layer can be formed by means of a thermal oxidation growing method.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a manufacturing method of a split-gate flash memory embedded in a logic circuit. Background technique [0002] Random access memory, such as DRAM and SRAM, has the problem of data loss after power failure during use. To overcome this problem, various nonvolatile memories have been designed and developed. Recently, flash memory based on the concept of floating gate has become the most common non-volatile memory due to its smaller cell size and good working performance. The non-volatile memory mainly includes two basic structures: a stack gate structure and a split gate structure. The stacked gate memory includes a floating gate oxide layer, a floating gate for storing electrons, an oxide / nitride / oxide (oxide-nitride-oxide, ONO) stack structure and a control electron storage layer sequentially formed on the substrate. and release the control gate. The split gate memory a...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/8247
Inventor 刘艳周儒领
Owner SEMICON MFG INT (SHANGHAI) CORP