Fin FET (field effect transistor) and manufacturing method of fin FET

Abstract

The invention discloses a fin FET (field effect transistor), which comprises an SOI (silicon on insulator) substrate, a fin-shaped grid electrode stack structure and a channel region, wherein the fin-shaped grid electrode stacking structure is arranged on the SOI substrate, the channel region is arranged between a source drain region and a source drain region arranged at the two sides of the grid electrode stacking structure in the SOI substrate, the source drain regions and the channel region extend in the first direction, and the grid electrode stacking structure extends in the second direction vertical to the first direction. The fin FET is characterized in that the source drain regions are metal silicide, the interface part between the source drain regions and the channel region also comprises doping ion segregation regions. According to the novel fin FET device and a manufacturing method of the novel fin FET device provided by the invention, doping ions are filled into the source drain of the metal silicide of the Fin FET, in addition, the annealing driving is carried out so that the doping ions are segregated at the interface part of the channel region, the fin FET source and drain resistance is effectively reduced, and meanwhile, the Schottky barrier height is also reduced, so the driving capability is improved.

Description

technical field [0001] The invention relates to a semiconductor device and a manufacturing method thereof, in particular to a fin field effect transistor capable of effectively reducing the Schottky barrier height and a manufacturing method thereof. Background technique [0002] The quasi-planar multi-gate FinFET (Fin Field Effect Transistor) structure compatible with the traditional production process has a thin gate Spacer and a strong gate-controlled source-drain electric field, which suppresses the short-channel effect, reduces the channel doping concentration, and achieves low off-state current and high drive current characteristics. For SOI substrates, lower loff can be obtained due to the reduction of source-drain and substrate leakage paths, and the fully depleted ultra-thin body structure reduces junction capacitance and good sub-threshold characteristics, and sub-10nm gate length devices can be realized. [0003] However, in the existing quasi-planar multi-gate Fi...

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Problems solved by technology

[0005] However, due to the high source/channel Schottky barrier height (SBH) of traditional Schottky barrier (SB) MOSFETs in the

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