Method for forming semiconductor structure

Abstract

The invention discloses a method for forming a semiconductor structure, comprising the steps: providing a substrate, wherein the surface of the substrate is provided with a layer to be etched; forming a mark layer on the layer to be etched, wherein a part of the mark layer is exposed out of the surface of the layer to be etched; performing plasma etching on the layer to be etched by using the mark layer as a mark to form an opening in the layer to be etched, wherein a radio frequency signal output from a bias radio frequency power source in the plasma etching is a pulse signal, the duty cycle of the pulse signal is reduced along with the increasing of the etching depth, when the bias radio frequency power source is powered on, a part of the layer to be etched is etched to form an etching hole in which an etching byproduct is provided, and when the bias radio frequency power source is powered off, the etching byproduct diffuses from the etching hole. The size of the opening formed by the plasma etching process is precious and even, and the opening etching rate is high.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a method for forming a semiconductor structure. Background technique [0002] With the development of integrated circuits to sub-micron dimensions, the integration level of devices continues to increase, while the size of devices continues to shrink, so the requirements for device dimensional accuracy are more stringent. In the manufacturing process of integrated circuits, conductive plugs are often used for electrical interconnection between conductive interconnection layers, or between device active regions and peripheral circuits, and play an important role in the composition of device structures. As the size of devices in integrated circuits shrinks and the degree of integration increases, the size of the vias used to form conductive plugs also decreases, and the aspect ratio of the vias increases accordingly, making the process of forming vias a challenge...

AI Technical Summary

Problems solved by technology

[0007] However, the size of the through holes formed by the existing plasma etching process is not uniform, resulting in poor morphology of the conductive plugs formed in the through holes, which may easily cause bridging of the conductive plugs in adjacent through holes, Or conductive plug open circuit and other problems

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