Semiconductor assembly with built-in stopper, and manufacturing method of same

Abstract

The invention relates to a semiconductor assembly with a built-in stopper, and a manufacturing method of the same. Accroding to one better embodiment, the method comprises arraning a semiconductor element onto a diaelectric layer by making a stopper serve as configuration guide member of the semiconductor element; adhering a reinforcement layer to the diaelectric layer; and forming a build-up circuit covering the semiconductor element, the stopper and the reinforcement layer to provide signal routing of the semiconductor element. Therefore, the stopper can accurately limit arrangement positions of the semiconductor element to avoid electrical connection failure between the semiconductor element and the build-up circuit.

Description

technical field [0001] The present invention relates to a semiconductor assembly and its manufacturing method, especially to a semiconductor assembly with built-in positioning parts and its manufacturing method. Background technique [0002] The market trend of electronic devices is to require thinner, smarter, and cheaper portable electronic devices. The semiconductor components used in the electronic devices need to further reduce their size and improve their electronics at a lower cost. performance. Among the various attempted methods, the module formed by embedding or building semiconductor chips in the printed circuit board is considered to be the most efficient method, which can greatly reduce the overall weight, thickness, and distance via internal connections. shortened to improve electronic performance. [0003] However, attempts to embed chips in circuit boards encounter many problems. For example, embedded chips can cause chip damage due to the thermal propertie...

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Problems solved by technology

[0003] However, attempts to embed chips in circuit boards encounter many problems. For example, embedded chips can cause chip damage due to the thermal properties of plastic materials when using adhesives for attachment and sealing / lamination processes. vertical and lateral displacement

Coefficient of thermal expansion (CTE) mismatch between metal, dielectric, and silicon at various thermal processing stages can lead to misalignment of build-up interconnect structures disposed thereon

U.S. Patent No. 7,935,893 to Tanaka et al.; U.S. Patent No. 7,944,039 to Aral; and U.S. Patent No. 7,405,103 to Chang disclose various alignment methods to address production yield issues, but none of the proposed methods provide An appropriate or effective method to control the displacement of the chip, which is due to the reflow of the adhesive under the chip when it is cured, so that the originally attached chip is misaligned in the predetermined setting position, even using highly accurate alignment The same problem occurs when marking and equipment

Chino's U.S. Patent Application No. 2010 / 0184256 discloses a resin sealing method, which uses an adhesive layer formed by fixing a semiconductor element on a support. This method can effectively control the chip from moving during the sealing process, but this The method does not provide any control or adjustment for the die attach process, and the dislocation of the die caused by the reflow of the adhesive used to attach the die is unavoidable

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