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Cutting and classifying method for wafer after BGA package is completed

A sizing and wafer technology, applied in laser welding equipment, electrical components, circuits, etc., can solve the problems of high energy attenuation, low cutting efficiency, high consumption, etc., achieve good cutting effect and efficiency, and low equipment maintenance costs , The effect of improving the cutting quality

Inactive Publication Date: 2014-06-25
HUIZHOU SPEED WIRELESS TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] (1) With the continuous advancement of integrated circuit manufacturing technology, Low K dielectric materials are used more and more widely in chips. Chipping, cracks, micro-loss, delamination and other problems caused by the mechanical force of the wafer and the stress of the wafer chip material itself have become increasingly prominent, seriously affecting the reliability level of the entire product after packaging
[0004] (2) Because of its complex sandwich structure layer, the cutting blade is easy to break and wear, and the cutting blade needs to be replaced when cutting about 2 to 4 wafers normally. high cost
[0005] (3) The cutting process needs to consume a lot of water for cooling and lubrication, which is not friendly to the environment
[0006] (4) The cutting speed is about 2-10mm / sec, the cutting efficiency is low, and the low production capacity leads to high cost, etc.
[0008]In the existing laser cutting technology for wafer cutting process, a very high energy laser is used to complete the cutting at one time, but there are the following disadvantages: the laser is With energy attenuation, high energy attenuation is fast, and the energy fluctuation is large, resulting in unstable cutting quality, especially for such sandwich-like wafer packaging products, which have glass layers, organic material layers, dielectric material layers and Silicon structure layers, especially glass layers and silicon structure layers, each layer requires different laser energy and needs to use different cutting parameters
At the same time, the more frequently the laser generator crystal is replaced, the higher the maintenance cost of the equipment

Method used

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  • Cutting and classifying method for wafer after BGA package is completed
  • Cutting and classifying method for wafer after BGA package is completed
  • Cutting and classifying method for wafer after BGA package is completed

Examples

Experimental program
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Effect test

Embodiment 1

[0038] against attached figure 1 The CIS image sensor chip with a thin silicon structure layer in the dicing line shown, the dicing and segregation method of the wafer after BGA packaging is completed, such as figure 2 and 3 shown, including steps:

[0039] (1) Attach UV tape 100 to the outer surface of the glass layer of the CIS wafer after wafer-level packaging is completed, with the glass layer facing down and the ball grid array facing up, and fixed on the laser processing equipment.

[0040] (2) if figure 2 As shown, the wafer is cut by laser 500 for the first time, and the structures that need to be cut include: the organic material protection layer 404 on the ball grid array surface, the thin silicon layer 401, the internal structure layer 403 of the wafer, and the organic material surrounding layer. Weir layer 300 . In the step of using laser to cut along the cutting line of the wafer ball grid array surface, the wafer is positioned according to the cutting line ...

Embodiment 2

[0045] Such as Figure 4 , 5 6 and 6 are respectively the schematic diagram of the silicon-free structure cutting line, the schematic diagram of the first laser cutting of the silicon-free structure cutting line, and the schematic diagram of the second laser cutting of the silicon-free structure cutting line. The specific cutting method is similar to Example 1.

Embodiment 3

[0047] Such as Figure 7 , 8 9 and 9 are respectively a schematic diagram of a dicing line with a thick silicon structure, a schematic diagram of the first laser cutting of a dicing line with a thick silicon structure, and a schematic diagram of a second laser cutting of a dicing line with a thick silicon structure. The specific cutting method is similar to Example 1.

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Abstract

The invention discloses a cutting and classifying method for a wafer after BGA packaging is completed. The method comprises the steps that the glass surface of the wafer after a wafer level packaging process is attached to UV adhesive tape first, an organic material protection layer, a silicon layer, a wafer internal structure layer, an organic material coffer layer and the like of an ball grid array surface are cut off by adopting lasers along a cutting line, only a glass layer is left, the glass layer is then cut with the lasers, finally sheet expanding processing is carried out by using sheet expanding equipment, each chip is classified, and a whole laser cutting process is completed. When the processing method is used for cutting off the materials of the organic material protection layer, a LowK dielectric material, a silicon structural layer, the organic material coffer layer and the like, no external stress acts in the process, the problems of edge breakage, tiny loss, layering and the like cannot be generated, the cutting and classifying quality of the chip can be guaranteed effectively, and improvement of cutting quality of the chip is facilitated greatly.

Description

technical field [0001] The invention relates to a semiconductor packaging process, in particular to a cutting and grading method for wafers after BGA packaging is completed by laser cutting. Background technique [0002] After the chip goes through the wafer-level packaging process, the product itself is similar to a sandwich structure, with a high-hardness silicon structure layer, a dielectric material layer, and a glass layer, as well as a soft organic film layer and a solder mask layer. This special structural layer brings many cutting problems to the traditional mechanical high-speed rotary blade cutting process: [0003] (1) With the continuous advancement of integrated circuit manufacturing technology, Low K dielectric materials are used more and more widely in chips. The traditional blade cutting process is caused by the mechanical force during processing and the stress of the wafer chip material itself. Problems such as edge chipping, cracks, micro-losses, and delam...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/78B23K26/38
CPCH01L21/78B23K26/38
Inventor 赖芳奇吕军
Owner HUIZHOU SPEED WIRELESS TECH CO LTD