Layering and reconfigurable on-chip network modeling and simulation system

Abstract

The invention discloses a layering and reconfigurable on-chip network modeling and simulation system. The system comprises a test layer, a main body layer and an operation layer. The core of the test layer is a reconfigurable rout unit and a network interface unit, and the test layer can change network structure parameters dynamically. The main body layer is mainly composed of a resource node unit, is provided with a universal OCP interface which is connected with the route unit through the network interface unit and integrates a flow generation mechanism unit, a receiving mechanism unit and a performance analysis logic unit. The operation layer is composed of a software configuration module, provides a good person-to-person interaction interface, and is used for flexible configuration and structure generation of the on-chip network structure feature parameters and communication modes. The layering and reconfigurable on-chip network modeling and simulation system can conduct modeling on an on-chip network architecture structure utilizing different topological structures, network sizes, routing algorithms, buffer area depths and the like, conduct network performance simulation under different communication models and communication loads, and provide a basis for the on-chip network architecture design under different application demands.

Description

technical field [0001] The invention belongs to the technical field of network-on-chip systems, and in particular relates to a hierarchical and reconfigurable network-on-chip modeling and simulation system. Background technique [0002] With the rapid development of integrated circuits and semiconductor process technologies, the scale of SoCs is getting larger and larger. Network-on-Chip (NoC), as a new method to solve the global communication problem in large-scale system-on-chip, can significantly improve the performance of the system, and is considered to be an inevitable direction for the development of multi-core technology in system-on-chip in the future. NoC design includes topology selection, routing algorithm determination, and basic component design. Different design schemes in each link have huge differences in performance. Therefore, it is particularly important to build a general reconfigurable network-on-chip system modeling and simulation system. important. ...

AI Technical Summary

Problems solved by technology

[0003] Existing NoC simulation platforms can be divided into two categories. One is designed in a high-level language, which can quickly model and analyze NoC performance. However, due to the high level of abstraction, the impact of the physical layer on performance is ignored, which will cause evaluation problems. The result deviates greatly from the actual situation; the other is to directly use the hardware description language to simulate the NoC system, but this method has poor flexibility and slow simulation speed, and cannot accurately and detailedly design the details of the network on chip (such as topology, flow rate, etc. model, etc.) for research

Moreover, although the above-mentioned network-on-chip performance evaluation models or simulators have their own characteristics, they all lack the ability to dynamically configure the test environment.

Images