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Method for manufacturing high withstand voltage super junction terminal structure

A junction terminal, high withstand voltage technology, applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve problems such as low withstand voltage, lower device reliability, avalanche breakdown, etc., to achieve improved breakdown voltage, reliable The effect of improved performance and strong current handling capability

Inactive Publication Date: 2014-10-15
UNIV OF ELECTRONIC SCI & TECH OF CHINA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, due to the limitations of process control, the withstand voltage of the terminal area is often lower than that of the cell area, so that avalanche breakdown occurs in the terminal area, which reduces the reliability of the device.

Method used

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  • Method for manufacturing high withstand voltage super junction terminal structure
  • Method for manufacturing high withstand voltage super junction terminal structure
  • Method for manufacturing high withstand voltage super junction terminal structure

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0030] This example includes the following steps:

[0031] Step 1: Epitaxial N- epitaxial layer 2 on N+ substrate 1, such as figure 2 shown;

[0032] Step 2: Using photolithography and bulk silicon etching processes, a plurality of shallow grooves 8 with a depth of h are formed on the upper layer of the N-epitaxial layer 2 in the terminal region II, as shown in image 3 shown;

[0033] Step 3: Using photolithography and bulk silicon etching process, perform deep groove etching in cell region I and terminal region II at the same time, and generate multiple deep grooves in the upper layer of N-epitaxial layer 2 in the cell region and terminal region respectively , the deep grooves in the terminal area should correspond to the shallow grooves 8 one by one, and the formed structure is as follows Figure 4 As shown, the depth of the deep groove 3 in the terminal area will be greater than that of the deep groove 4 in the cell area, and the total depth difference is the depth h o...

Embodiment 2

[0044] Such as Figure 13 As shown, the difference between this example and Example 1 lies in that the semiconductor pillars 8 of the second conductivity type in the terminal region II are connected. The preparation method of this example only needs to change the pattern of the mask plate for bulk silicon etching in step 2, and the rest of the steps are the same as in the first embodiment.

Embodiment 3

[0046] Such as Figure 14 As shown, the difference between this example and the first example lies in that the semiconductor pillars 8 of the second conductivity type in the terminal region II are partially connected. The preparation method of this example only needs to change the pattern of the mask plate for bulk silicon etching in step 2, and the rest of the steps are the same as in the first embodiment.

[0047] The invention is also applicable to the preparation of P-channel super-junction VDMOS devices, super-junction DIODE or super-junction IGBT.

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PUM

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Abstract

The invention relates to the technical field of semiconductor process manufacture and specifically relates to a method for manufacturing a high withstand voltage super junction terminal structure. The method includes, by means of two times of etch processes and once epitaxy filling process, forming in a terminal area a semiconductor column, deeper than a cellular area, in a second conductive type, and introducing a field limiting ring structure to the top end of the semiconductor column in the second conductive type in the terminal area. The method for manufacturing the high withstand voltage super junction terminal structure has the advantages of being capable of increasing breakdown voltage of the terminal area so that avalanche breakdown occurs in the cellular area; since the cellular area has higher current processing capability, reliability of devices are improved; the method is particularly applicable to manufacturing the high withstand voltage super junction terminal structure.

Description

technical field [0001] The invention belongs to the technical field of semiconductor process manufacturing, and in particular relates to a preparation method of a high withstand voltage super junction terminal structure. Background technique [0002] At present, the application fields of power MOSFET devices are becoming wider and wider, and are widely used in DC-DC converters, DC-AC converters, power amplifiers and other fields. Vertical double-diffused metal-oxide-semiconductor field-effect transistor (VDMOS) has the advantages of fast switching speed, low loss, high input impedance, low driving power, good frequency characteristics, and highly linear transconductance, and has become the most widely used power device at present. [0003] For VDMOS, its breakdown voltage BV is mainly determined by the drift region. The thicker the drift region, the lower the doping concentration, the higher the breakdown voltage, however, while the breakdown voltage increases, its on-resis...

Claims

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Application Information

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IPC IPC(8): H01L21/336
CPCH01L29/0638H01L29/66712
Inventor 任敏王为姚鑫吴玉舟许高潮李泽宏张金平高巍张波
Owner UNIV OF ELECTRONIC SCI & TECH OF CHINA
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