Method for manufacturing selective tensile stress contact hole etching stop layers

Abstract

The invention discloses a method for manufacturing selective tensile stress contact hole etching stop layers. The method comprises the steps that a high tensile stress silicon nitride layer is deposed on an MOS device to be used as a contact hole etching stop layer, a multiple-laminating layer composed of a silicon nitride layer and a silicon oxide layer in an alternative mode is used as a ultraviolet light blocking layer of a PMOS area, the high tensile stress silicon nitride layer on the PMOS area and an NMOS area is subjected to selective ultraviolet light polymerization processing, a high tensile stress silicon nitride layer with the relative low stress covers the PMOS area, a high tensile stress silicon nitride layer with the relative high stress covers the NMOS area, and the purpose that the PMOS area and the NMOS area are provided with selective silicon nitride contact hole etching stop layers with different high tensile stress is achieved, the negative influence on the hole mobility of a PMOS device of single-step high tensile stress silicon nitride deposition is avoided, the complexity of a process for forming two contact hole etching stop layers by two-step silicon nitride deposition is also avoided, and the electrical property of the device is improved by low cost.

Description

technical field [0001] The invention relates to the technical field of semiconductor integrated circuit manufacturing, and more specifically, to a method for manufacturing a selective tensile stress contact hole etching stop layer based on strained silicon technology and improving device performance through high-stress silicon nitride. Background technique [0002] With the development of CMOS integrated circuit manufacturing process and the reduction of critical dimensions, many new methods are applied to device manufacturing process to improve device performance. Among them, the high-stress silicon nitride film is introduced into the integrated circuit manufacturing process because it can effectively improve the carrier mobility of the MOS tube, thereby increasing the operating speed of the device. The compressive stress in the direction of the PMOS channel can improve the hole mobility in the PMOS device, and the tensile stress in the direction of the NMOS channel can imp...

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Problems solved by technology

[0006] However, the Single CESL process is used to simultaneously form a high tensile stress silicon nitride contact hole etch stop layer with ultimate stress in the PMOS region and NMOS region after UV curing, and the existence of the high tensile stress silicon nitride with ultimate stress has a negative effect on The electrical performance of PMOS devices is adversely affected, so the Single CESL process is a compromise method at the expense of hole mobility in PMOS devices.

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