Method for eliminating alloy surface bulge on junction area of top metal layer

Abstract

The invention provides a method for eliminating alloy surface bulge on a junction area of a top metal layer. The method includes the steps of forming a semiconductor device on a substrate and forming metal interconnect layers on the semiconductor device; depositing at least one passivation layer on the topmost one of the metal interconnect layers, as a protective layer; annealing and alloying the topmost one of the metal interconnect layers under protection of the passivation layer; etching the passivation layer to exposure the junction area of the topmost one of the metal interconnect layer. Compared with the prior art, the method has the advantages that the topmost one of the metal interconnect layers is annealed and alloyed under protection of the passivation layer, wires and the junction area can be bonded together better, stable yield and stable electrical property can be maintained, and production cost can also be reduced.

Description

technical field [0001] The invention relates to the field of chip manufacturing, in particular to a method for eliminating the bulge on the alloy surface of the bonding area of ​​the top metal layer. Background technique [0002] In the final stage of the existing chip manufacturing process, when the topmost metal interconnection layer (aluminum-copper) of the semiconductor device is made, then the passivation layer is deposited and etched on the topmost metal interconnection layer. After the etching of the chemical layer, the bulk of the topmost metal interconnection layer is exposed as a bonding area, which provides metal contacts for subsequent packaging and testing, thereby realizing the input and output of voltage and current. see Figure 1(a) and Figure 1(b) , which are schematic diagrams of the planar and cross-sectional structures of the bonding region of the topmost metal interconnection layer under an electron microscope, respectively, in the prior art. Such as ...

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Problems solved by technology

like Figure 1(a) and Figure 1(b) As shown, there are many alloy bumps 112 (indicated by arrows in the figure) on the surface of the pad metal bonding area where the topmost metal interconnection layer 110 is in contact with the package test lead 111, and the analysis found that the alloy bumps 112 The formation is related to the release of the internal stress of aluminum and copper. The alloy bumps 112 on the surface of the bonding area will adversely affect the subsequent packaging and testing, affecting the contact and bonding between the wire and the bonding area, and ultimately affecting the yield and chip reliability. electrical performance, thereby increasing production costs

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