Method for preparing barrier layer for nickel-silicon alloying process

Abstract

The invention provides a preparation method for a barrier layer used for a nickel-silicon alloying process. The method includes the following steps: providing a semiconductor substrate which is provided with a barrier layer area and a non-barrier-layer area; forming a first oxidation layer on the surface of the semiconductor substrate; forming a nitride layer on the surface of the first oxidation layer; removing the nitride layer on the barrier layer area through a photoetching and etching process so as to expose the first oxidation layer on the barrier layer area; forming a second oxidation layer on the semiconductor substrate which completes step 04; and removing the second oxidation layer and the nitride layer on the non-barrier-layer area via the photoetching and etching process, wherein the first oxidation layer and the second oxidation layer are used together as a barrier layer. Through adopting the second oxidation layer to substitute the nitride layer in the barrier area, happening of a phenomenon of tunneling of free electrons, caused by existence of an interface of the nitride layer and the oxidization layer is prevented and the charge maintenance performance of a device is improved.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a method for preparing a barrier layer used in a nickel-silicon alloying process. Background technique [0002] With the development of semiconductor manufacturing technology, the reduction of the size of the device causes the contact resistance to increase. In order to reduce the contact resistance, the metal alloying process has been widely used. Especially at 65nm and below, nickel has been commonly used to react with silicon materials to form silicide or salicide on semiconductor structures, thereby forming low-resistance regions. [0003] Usually, see figure 1 , which is a schematic flow chart of an existing method for forming a nickel-silicon alloy, which specifically includes the following steps: [0004] Step L01: sequentially deposit an oxide layer and a nitride layer as a barrier layer on the semiconductor substrate; the semiconductor substrate can have any str...

AI Technical Summary

Problems solved by technology

[0008] In the 55nm high-voltage CMOS (HVCMOS) logic process, the barrier layer in the above nickel-silicon alloying process usually adopts an oxygen / nitride film stack structure (ON structure). It forms a parasitic memory device similar to SONOS with the lower floating gate (FG); when the lower floating gate is subjected to high-voltage programming, free electrons can easily tunnel into the ON structure interface of the upper layer of the floating gate, thereby affecting the charge retention performance of the floating gate and reducing the charge of the device storage capacity

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