Junctionless transistor and method of making the same

Abstract

The invention provides a non-junction transistor and a manufacturing method of the non-junction transistor. The non-junction transistor comprises a substrate, fins, a grid electrode structure, a source element and a drain electrode, wherein the fins are formed on the base, the cross section of the top of each fin in a direction vertical to the fin extending direction is in a semicircular shape, each fin is provided with doping ions of a first doping type, in addition, the ion concentration is progressively decreased from the fin surface to the fin center, the grid electrode structure transversely spanning across the fins, and the source electrode and the drain electrode are positioned in the fins arranged at two sides of the grid electrode structure, and have doping ions of a first doping type. The manufacturing method comprises the steps that the substrate is provided; the substrate is visualized, and the fins are formed; the top of each fin is subjected to at least once rounding processing, so that the cross section of the top of each fin in the direction vertical to the fin extending direction is in a semicircular shape; each fin is subjected to ion doping of the first doping type, so that the ion concentration is progressively decreased from the fin surface to the fin center; the grid electrode structure transversely spanning across the fins is formed on the fins; the ion doping of the first doping type is carried out on the fins arranged at two sides of the grid electrode structure, and the source electrode and the drain electrode are formed. The non-junction transistor and the manufacturing method have the advantage that the short channel effect can be inhibited.

Description

Technical field [0001] The present invention relates to the field of semiconductor technology, in particular to a junctionless transistor and a manufacturing method thereof. Background technique [0002] In order to keep up with Moore's Law, people continue to shrink the feature size of MOSFET transistors. Doing so can bring benefits such as increased chip density and improved switching speed of MOSFET. As the channel length of the device is shortened, the distance between the drain and the source is also shortened. As a result, the gate's ability to control the channel becomes worse and the gate voltage pinch off the channel becomes more difficult. The larger the value, the more likely to occur subthreshold leakage (Subthreshold leakage), the so-called short-channel effects (short-channel effects, SCE) are more likely to occur. [0003] For this reason, planar CMOS transistors are gradually transitioning to a three-dimensional (3D) fin field effect transistor (Fin Field Effect T...

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Problems solved by technology

[0005] However, as the feature size further decreases, the short channel effect of existing FinFETs is gradually highlighted

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