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A super junction device fabrication process

A preparation process and device technology, applied in the field of superjunction device preparation technology, can solve the problems of difficult trench technology, uneven PN interface, and difficult consistency.

Active Publication Date: 2017-08-29
CHINA RESOURCES MICROELECTRONICS (CHONGQING) CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

This method is simpler than the multiple epitaxy process, and also reduces the cost, but it is difficult to fill the deep trench epitaxy, and the process of etching a trench with a large aspect ratio is difficult and requires expensive equipment.
[0006] For this reason, in some existing technologies, various new process methods have been proposed on the basis of deep trench epitaxy, which can reduce the process difficulty of preparing super junctions, but it is difficult to make P-type semiconductor materials in the epitaxy process of P-type semiconductor materials. The vertical side of the material is flat, resulting in the unevenness of the PN interface after the epitaxial N-type semiconductor material, which will affect the reverse withstand voltage
In addition, it is difficult to precisely control the width of P-type semiconductor materials and N-type semiconductor materials through epitaxy, and it is difficult to reduce the cell area

Method used

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  • A super junction device fabrication process
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  • A super junction device fabrication process

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Embodiment 1

[0035] A semiconductor substrate having a first conductivity type is provided. Optionally, the semiconductor substrate includes a base substrate 110 and a buffer layer 120 covering the base substrate 110 , and the ion doping concentration of the buffer layer 120 is lower than the ion doping concentration of the base substrate 110 . A sacrificial layer 130, a first dielectric layer 140, a second dielectric layer 150 and a photoresist (PR) 160 are sequentially formed on the semiconductor substrate from bottom to top. The formed structure can be referred to Figure 2Ashown. Optionally but not limited, the first dielectric layer 140 is a DARC (dielectric Anti-reflective coating, dielectric anti-reflective coating) layer, and the second dielectric layer 150 is a BARC (Bottom Anti Reflective coating, bottom anti-reflective coating) layer. In some embodiments, a layer of SiON may be deposited by CVD process as the above-mentioned DARC layer. Optionally but not limited, the aforemen...

Embodiment 2

[0047] This embodiment provides a semiconductor device manufacturing process, including the following steps:

[0048] Step S1: firstly etching a sacrificial layer to form a plurality of first grooves spaced apart from each other in the sacrificial layer. Optionally but not limited, the sacrificial layer is made of amorphous carbon, and the sacrificial layer is etched by using photolithography and etching processes, so as to form a plurality of first trenches spaced apart therein.

[0049] Step S2: preparing a side wall to cover the side wall of the first trench. Optionally but not limited, the sidewall can be made of silicon oxide or silicon nitride. The steps of preparing the sidewall mainly include: first depositing a sidewall material layer to cover the exposed surface of the device, and then using an anisotropic etching process to etch the sidewall material layer to retain the Side walls on side walls.

[0050] Step S3: epitaxially growing a first epitaxial layer of a f...

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Abstract

The present invention disclosed a super -knot device preparation process, including the following steps: providing a semiconductor substrate with a first -electrical type, and preparing a sacrifice layer with several first grooves on the semiconductor substrate;On the side wall of the first groove; prepare the first external layer of the first electrical type to fill the first groove; remove the sacrifice layer and the side wall to form a second groove in the first extension of the first extension;The second external layer of the second -conductive type is filled with the second groove.By adopting the advanced non -fixed carbon process, the invention makes the super -structured N -type semiconductor material and P -type semiconductor material vertical and flat, and the width of N -type semiconductor materials and P -type semiconductor materials is accurate and consistentEssenceAnd due to the advanced non -fixed carbon process, the width of the P -pillar and N pillars can be reduced to less than 40nm, which greatly reduces the cell area.

Description

technical field [0001] The present invention relates to the field of semiconductor preparation, specifically, to a super junction device preparation process. Background technique [0002] In the field of high-voltage MOSFETs (400V ~ 1000V), the super junction (Super Junction) structure, as an advanced drift region structure, has attracted more and more attention from the industry. The drift region of the super-junction structure uses an alternate PN junction structure to replace the single conductivity type drift region in the traditional high-voltage MOSFET, and a lateral electric field is introduced in the drift region, so that the device drift region can be completely exhausted at a small turn-off voltage, and the strike The breakdown voltage is only related to the thickness of the depletion layer and the critical electric field. Therefore, under the same withstand voltage, the doping concentration of the drift region of the super-junction structure can be increased by a...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/336
CPCH01L29/66477H01L29/0634H01L29/7802H01L29/66712
Inventor 黄晓橹
Owner CHINA RESOURCES MICROELECTRONICS (CHONGQING) CO LTD