A master-slave flip-flop based on finfet device

Abstract

The invention discloses a master-slave flip-flop based on a FinFET transistor. The master-slave flip-flop based on the FinFET transistor is that a first P type FinFET pipe, a second P type FinFET pipe, a first N type FinFET pipe, a second N type FinFET pipe, a third N type FinFET pipe, a fourth N type FinFET pipe, a fifth N type FinFET pipe, a sixth N type FinFET pipe and a seventh N type FinPET pipe form a master latch; a slave latch comprises a second phase inverter and a third phase inverter, wherein the second phase inverter consists of a third P type FinFET pipe and an eighth N type FinFET pipe; the third phase inverter consists of a fourth P type FinFET pipe and a ninth N type FinFET pipe; the slave lock is a loop composed of two phase inverters. The master-slave flip-flop based on the FinFET transistor has the advantages that the circuit structure is simple, the power consumption and spreading delay are small, the 32nm process device parameters of a PTM model are adopted for simulating under a standard voltage (1v) condition; compared with the existing flip-flop, the master-slave flip-flop has the advantages that the circuit power consumption is reduced by about 60%, and the spreading delay is reduced by about 46%.

Description

technical field [0001] The invention relates to a flip-flop, in particular to a master-slave flip-flop based on a FinFET device. Background technique [0002] At present, the design process of integrated circuit technology has entered the nanometer stage. In the chip design process, whether considering the cost and performance of the chip itself or the market of electronic information products, the power consumption has become an important indicator to measure the performance of the chip. . Low power consumption design has become a hot spot and difficulty in current chip design. [0003] As the size of transistors continues to shrink, limited by the short-channel effect and the current manufacturing process, the space for reducing the size of ordinary CMOS transistors is extremely narrowed. When the size of an ordinary CMOS transistor is reduced to below 20nm, the leakage current of the CMOS transistor will increase sharply, resulting in a large leakage power consumption o...

AI Technical Summary

Problems solved by technology

The circuit diagram of the multi-way switch type master-slave flip-flop is as follows: figure 1 As shown, the flip-flop has the following problems: 1. The number of FinFET transistors used is large, the circuit structure is complex, the layout area is large and the circuit power consumption will be large; 2. The clock signal connected to the circuit needs to be driven Four FinFET transmission gates, the clock signal load is very large, resulting in a large circuit power consumption and propagation delay, the propagation delay of the circuit is the sum of the delay of a FinFET transmission gate and the delay of a FinFET inverter

The circuit diagram of the forced pulse master-slave flip-flop is as follows: figure 2 As shown, the number of transistors used by this flip-flop is reduced compared with the multi-way switching master-slave flip-flop, the clock signal only needs to drive two FinFET transmission gates, and the clock load is reduced, but the flip-flop has the following problems: the flip-flop locks The change of the state of the memory requires a strong input data pulse, and the short DC path causes a large static power consumption, which leads to a large power consumption

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