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Multi-chip laminating type packaging structure and packaging method thereof

A packaging structure and packaging method technology, applied in the direction of semiconductor/solid-state device components, semiconductor devices, electrical components, etc., can solve the problems affecting the performance of the finished device, large volume, increased resistance and thermal resistance, etc., to achieve conduction loss and switching. The effect of reduced losses, better performance, and enhanced heat dissipation efficiency

Active Publication Date: 2015-06-03
ALPHA & OMEGA SEMICON INT LP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, for a specific packaging structure, the above-mentioned high-end MOSFET chip, low-end MOSFET chip and controller chip can only be arranged in parallel on the same plane of the lead frame, so the volume after packaging is large; moreover, they are only connected by wires The corresponding pins of the chip (for example, between the source S1 of the HS and the drain D2 of the LS) will increase the resistance and thermal resistance, which will affect the performance of the finished device

Method used

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  • Multi-chip laminating type packaging structure and packaging method thereof
  • Multi-chip laminating type packaging structure and packaging method thereof
  • Multi-chip laminating type packaging structure and packaging method thereof

Examples

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Embodiment 1

[0067] Cooperate see Figure 1A~Figure 1C As shown, in the present invention, two MOSFET chips of the same type (two N-type or two P-type) are used as high-end MOSFET chips (referred to as HS chips 20 for short) and low-end MOSFET chips (referred to as LS chips 30 for short). A controller chip (abbreviated as IC chip 50) is stacked on the same plane where the two MOSFET chips are located through a connecting sheet 40, and the IC chip 50 is connected to the corresponding electrodes of the LS chip 30 and the HS chip 20 and After the pins 14 are connected, they are packaged in the same plastic package 100 to form a DC-DC converter.

[0068] The HS chip 20 and the LS chip 30 are respectively provided with a source and a gate on the front of the chip, and a drain is provided on the back of the chip; wherein, the gate G1 of the HS chip 20 and the gate G2 of the LS chip 30 are both It is connected with the control pole on the IC chip 50; the drain D1 of the HS chip 20 is connected t...

Embodiment 2

[0094] Figure 4A~Figure 4G It shows the schematic structure in each step of chip packaging in this embodiment, Figure 5 The flow of the encapsulation method in this embodiment is shown. Wherein, the structure of this embodiment is briefly described as follows, that is, a lead frame 10 ( FIG. 4A ) is provided, including a first loading stage 11, which is used to fixedly connect the HS chip 20 and form an electrical connection with the back drain D1 ( Figure 4B ); also includes a second carrier stage, which is provided with a first part 12 and a second part 13, which are used to fix and connect the flipped package LS chip 30 and form an electrical connection with the source S2 and the gate G2 on the front side respectively ( Figure 4C ). A connecting piece 40 is conductively connected on the HS chip 20 and the LS chip 30, so that the high-side connection portion 41 of the connecting piece 40 is electrically connected to the source S1 on the front side of the HS chip 20, an...

Embodiment 3

[0098] Figure 6A ~ Figure 6G It shows the schematic structure in each step of chip packaging in this embodiment, Figure 7The flow of the encapsulation method in this embodiment is shown. Among them, the structure of this embodiment is briefly described as follows, that is, a lead frame 10 ( FIG. 6A ) is provided, including a first loading stage 11, which is used for fixedly connecting the HS chip 20 and forming an electrical connection with the back drain D1 ( Figure 6B ); also includes a second carrier stage, which is provided with a first part 12 and a second part 13, which are used to fix and connect the flipped package LS chip 30 and form an electrical connection with the source S2 and the gate G2 on the front side respectively ( Figure 6C ). A connecting piece 40 is conductively connected on the HS chip 20 and the LS chip 30, so that the high-side connection portion 41 of the connecting piece 40 is electrically connected to the source S1 on the front side of the HS ...

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PUM

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Abstract

The invention relates to a multi-chip laminating type packaging structure and a packaging method thereof. The packaging structure has the advantages that a source of an HS chip and a drain of an LS chip are electrically connected by a connecting sheet, so the conductive loss and switch loss are reduced, and the heat dissipation efficiency is improved; an IC (integrated circuit) chip is connected with the connecting sheet in an insulating way, and the IC chip can be laminated above the planes of the HS chip and the LS chip, so as to effectively reduce the size of the packaged device; the bottom surfaces of a first chip carrying table and a second chip carrying table are exposed out of a plastic packaging body; multiple methods are set, and the surface of one part, not connecting with the IC chip, of the connecting sheet is exposed out of the plastic packaging body; or the connecting sheet is further connected with a heat radiating plate, and the surface of one part of the heat radiating plate is exposed out of the plastic packaging body; or the heat insulating plate is inserted into a reserved notch of the plastic packaging body, so as to touch the connecting sheet and radiate the heat.

Description

technical field [0001] The invention relates to the field of semiconductors, in particular to a multi-chip stacked package structure and a package method thereof. Background technique [0002] In a DC-DC (direct current-direct current) converter, there are usually two MOSFETs (metal oxide semiconductor field effect transistors) as switching switches, one is a high-end MOSFET (referred to as HS), and the other is a low-end MOSFET (abbreviated as LS). ). Among them, the gate G1 of HS and the gate G2 of LS are connected to a controller (abbreviated as IC); the drain D1 of HS is connected to the Vin terminal, the source S1 is connected to the drain D2 of LS, and the source S2 of LS is connected to Gnd terminal to form the DC-DC converter. [0003] For the chip packaging structure in the DC-DC converter, it is hoped that the high-end MOSFET chip, the low-end MOSFET chip and the controller chip will be packaged in the same plastic package, so as to reduce the number of periphera...

Claims

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Application Information

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IPC IPC(8): H01L23/495H01L23/367H01L25/07H01L21/60
CPCH01L23/3672H01L23/4922H01L23/49562H01L23/49568H01L24/84H01L25/072H01L23/3107H01L23/49531H01L23/49575H01L25/16H01L25/50H01L2924/181H01L2224/0603H01L2224/05554H01L2224/05553H01L2224/48137H01L2224/48247H01L2224/32245H01L2224/37H01L2224/37147H01L2224/40137H01L2224/40139H01L2224/40095H01L2224/40H01L2224/40245H01L2224/73265H01L2224/49111H01L2224/8385H01L2224/84986H01L2224/8485H01L2924/13091H01L2924/13055H01L2924/00H01L2924/00012H01L24/40H01L24/37H01L24/48H01L2224/84345H01L2224/73221H01L2924/00014
Inventor 张晓天潘华鲁明朕鲁军哈姆扎·依玛兹
Owner ALPHA & OMEGA SEMICON INT LP
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