Rapidio controller using window mapping mechanism and its control method

A technology of mapping mechanism and control method, applied in the direction of instrumentation, electrical digital data processing, etc., can solve problems that cannot be solved by processors

Active Publication Date: 2018-04-20
AVIC NO 631 RES INST
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

But because the bridge chip usually only corresponds to one other standard bus, it cannot universally solve this problem for all types of processors, and not all processors can find a suitable bridge chip as a solution

Method used

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  • Rapidio controller using window mapping mechanism and its control method
  • Rapidio controller using window mapping mechanism and its control method
  • Rapidio controller using window mapping mechanism and its control method

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Experimental program
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Embodiment Construction

[0067] This controller is realized by using FPGA with high-speed serial transceiver as the platform and carrying out secondary development on the basis of conventional RapidIO programmable logic IP Core. The front end of the controller is a parallel local bus, and the back end is The high-speed serial interface of the RapidIO interface adopts the mechanism of address window mapping to realize the mutual conversion between the parallel local bus operation and the RapidIO bus operation.

[0068] The hardware composition of this controller is as attachedfigure 1 shown. The controller is obtained through secondary development on the conventional RapidIO programmable logic IPCore, attached figure 1 The square module in the middle on the right is the RapidIO IP Core, which realizes the mutual conversion between the high-speed serial code on the physical link and the parallel data signal in the RapidIO packet format. RapidIO IPCore mainly has six external interfaces, namely "configu...

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Abstract

The present invention proposes a RapidIO controller using a window mapping mechanism, including a RapidIO IP Core, a parallel local bus interacting with an external processor, an address decoding module, an extended configuration space, an initiator request packet generation module, and an initiator response packet analysis module and the recording module that initiates the bus request; the address decoding module decodes the read and write operation chip selection on the parallel local bus to each subsequent stage according to the chip selection information of each address space provided by the configuration register group in the extended configuration space Accessed resources; the initiator request packet generation module is responsible for constructing the request packet when a RapidIO bus request needs to be initiated; the initiator response packet parsing module parses the response packet received after the controller initiates the RapidIO bus request; the record module for initiating the bus request Record the RapidIO bus request initiated by the controller that needs a response packet. The invention adopts the RapidIO controller and the control method of the window mapping mechanism, has good compatibility and complete functions.

Description

technical field [0001] The invention belongs to the field of embedded computing systems, in particular to a RapidIO controller adopting a window mapping mechanism and a control method thereof. Background technique [0002] With the continuous development of integrated avionics systems, on the one hand, the system has higher requirements for the rate and scale of data exchange and data transmission between various internal functional modules. The traditional parallel bus is due to the clock frequency and signal routing. On the other hand, due to the increasing scale of the system, based on the higher requirements for system fault tolerance and system network reconfiguration, the commonly used tree bus structure is no longer suitable for the entire system. architecture model. Based on such application requirements and development trends, the avionics system needs to introduce a new interconnection communication architecture to solve these problems. [0003] RapidIO technolog...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F13/20
Inventor 段小虎李鹏韩强邓豹解文涛魏巍赵小冬邹晨袁迹周啸代明清
Owner AVIC NO 631 RES INST
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