Transistor forming method
A technology of transistors and stop layers, applied in semiconductor devices, semiconductor/solid-state device manufacturing, electrical components, etc., can solve problems such as unstable performance of high-k metal gate transistors
Active Publication Date: 2015-07-01
SEMICON MFG INT (SHANGHAI) CORP
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Problems solved by technology
[0005] However, the performance of high-K metal gate transistors formed by the prior art is not stable
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[0029] As mentioned in the background art, the performance of the high-K metal gate transistor formed in the prior art is unstable.
[0030] After research, it is found that the current process for forming high-K metal gate transistors is a gate-last process (Gate Last), and the gate-last process will cause damage to the size of the formed gate structure. For details, please refer to Figure 2 to Figure 4 , Figure 2 to Figure 4 is a form such as figure 1 The schematic cross-sectional structure diagram of the process of the gate structure 110 is shown.
[0031] Please refer to figure 2 , providing a substrate 100, the surface of the substrate 100 has a dummy gate structure 120, and the dummy gate structure 120 includes: a dummy gate dielectric layer 121 located on the surface of the substrate, a dummy gate located on the surface of the dummy gate dielectric layer 121 layer 122, and spacers 123 on the surface of the substrate 100 on both sides of the dummy gate layer 122 a...
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A transistor forming method comprises the steps of providing a substrate, wherein the surface of the substrate is of a pseudo gate electrode structure, and the pseudo gate electrode structure comprises a pseudo gate dielectric layer located on the surface of the substrate and a pseudo gate electrode layer located on the surface of the pseudo gate dielectric layer; forming stop layers on the surfaces of the substrate and the pseudo gate electrode structure, wherein doped ions exist in the stop layers; forming dielectric layers on the surfaces of the stop layers, wherein the surfaces of the dielectric layers are flush with the surface of the stop layer located at the top of the pseudo gate electrode layer; removing the stop layer located at the top of the pseudo gate electrode layer, the pseudo gate electrode layer and the pseudo gate dielectric layer, wherein an opening is formed in the dielectric layers; forming a gate dielectric layer and a gate electrode layer in the opening, wherein the gate dielectric layer is located on the side wall and the surface of the bottom of the opening, and the gate electrode layer is located on the surface of the gate dielectric layer and filled in the opening. A formed transistor is stable in performance and good in appearance and shape.
Description
technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a method for forming a transistor. Background technique [0002] With the rapid development of integrated circuit manufacturing technology, the size of semiconductor devices in integrated circuits, especially MOS (Metal Oxide Semiconductor, metal-oxide-semiconductor) devices, has been continuously reduced to meet the miniaturization and development of integrated circuits. Integration requirements. In the process of continuous shrinking of the size of MOS transistor devices, the process of using silicon oxide or silicon oxynitride as the gate dielectric layer in the existing process is challenged. Transistors formed with silicon oxide or silicon oxynitride as the gate dielectric layer have some problems, including increased leakage current and diffusion of impurities, which affect the threshold voltage of the transistor and further affect the performance of se...
Claims
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Login to View More IPC IPC(8): H01L21/336H01L21/28
CPCH01L29/4232H01L29/66545
Inventor 禹国宾
Owner SEMICON MFG INT (SHANGHAI) CORP