A kind of semiconductor device and its preparation method

Abstract

The present invention relates to a semiconductor device and a manufacturing method thereof, the method comprising: providing a semiconductor substrate, an interlayer dielectric layer is formed on the semiconductor substrate, a contact hole is formed in the interlayer dielectric layer, and photolithography mark holes, the photolithography mark holes have gaps; deposit a sacrificial material layer to completely fill the gaps; form a protective layer on the interlayer dielectric layer and the sacrificial material layer; Forming through-silicon holes in the bottom and the interlayer dielectric layer; removing the protection layer to expose the sacrificial material layer; removing the sacrificial material layer to expose the gap. The present invention proposes to use a-C as the protective layer of CT in the TSV VIA middle process. Compared with SIN, a-C has better step coverage ability and can be completely removed, so as not to affect the subsequent first metal Layer lithography (M1photo) alignment effectively solves the problem of OVL measurement.

Description

technical field [0001] The invention relates to the field of semiconductors, in particular, the invention relates to a semiconductor device and a preparation method thereof. Background technique [0002] In the field of electronic consumption, multi-function devices are more and more popular among consumers. Compared with devices with simple functions, the production process of multi-function devices will be more complicated, such as the need to integrate multiple chips with different functions on the circuit board, so 3D integrated circuit (integrated circuit, IC) technology, 3D integrated circuit (integrated circuit, IC) is defined as a system-level integrated structure, stacking multiple chips in the vertical plane direction, thereby saving space, the edge of each chip Multiple pins can be drawn out as needed, and these pins can be used to interconnect the chips that need to be connected to each other through metal wires, but the above method still has many shortcomings, ...

AI Technical Summary

Problems solved by technology

Perform the TSV process after forming the contact hole, refer to Figure 1b , forming a protective layer 105 on the interlayer dielectric layer 102, on the pattern of the contact hole 103, and in the photomark pattern (photo mark) 104. At present, in the semiconductor process, SiN is usually deposited by CVD as the protective layer, The method and cost are relatively mature and simple. In the Cu-Cu bonding process (TSV VIAmiddle) in wafer bonding, it is usually used as the protective layer of CT and the stop layer of TSVCMP. However, due to the poor step filling of SiN ( Step coverage) ability, in the area of ​​the photo mark pattern (photo mark) can not be well filled, there are still large gaps; pattern the interlayer dielectric layer 102 to form through silicon via grooves, such as Figure 1c As shown, wherein the protection layer 105 forms a good protection for the CT region; then deposits a through-silicon via isolation layer 106 (TSV isolation), and the through-silicon via isolation layer 106 has a good step coverage (step coverage) capability , therefore, the void in the photolithography mark hole region (CTphoto mark) is completely filled, as Figure 1d As shown, conductive material is then filled in the TSV groove and planarized to the protective layer 105 to form a TSV structure, such as Figures 1e-1f As shown; the protective layer 105 is finally removed, but after removal, the TSV release layer 106 (oxide) remains in the lithography mark hole area (CT photo mark) and cannot be removed, so that the subsequent first metal layer lithography ( M1photo) process alignment CT becomes difficult, and it is not conducive to the measurement of alignment (OVL)

[0007] In the prior art, SIN is usually deposited by CVD as a protective layer, and the method and cost are relatively mature and simple. In the TSV VIA middle process, it is also usually used as a protective layer for CT and a stop layer for TSV planarization. The CT pattern of the photo mark (photo mark) and the aperture of the contact hole as an interconnection have a huge CD difference, resulting in more dielectric residues in the CT pattern of the photo mark (photo mark) during the TSV process. It is an inevitable problem in TSV VIAMiddle process SIN as a protective layer, and there is no good solution for the time being

[0008] In addition, using SIN as the protective layer of CT in the TSV process will bring some process problems, so that the subsequent M1 photolithography process photolithography (photo) cannot be aligned and aligned (OVL) and cannot be measured. How to solve this problem is The biggest challenge facing the current TSV process

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