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VDMOS structure inhibiting parasitic transistor from opening and manufacture method of VDMOS structure

A parasitic transistor, polysilicon gate technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., to achieve the effect of reducing electric field strength, high reliability, and changing electric field distribution

Inactive Publication Date: 2015-07-08
BEIJING ZHONGKE XINWEITE SCI & TECH DEV
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0007] The present invention aims to solve the problems described above

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  • VDMOS structure inhibiting parasitic transistor from opening and manufacture method of VDMOS structure
  • VDMOS structure inhibiting parasitic transistor from opening and manufacture method of VDMOS structure
  • VDMOS structure inhibiting parasitic transistor from opening and manufacture method of VDMOS structure

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Embodiment Construction

[0026] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments It is a part of embodiments of the present invention, but not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention. It should be noted that, in the case of no conflict, the embodiments in the present application and the features in the embodiments can be combined arbitrarily with each other.

[0027] A schematic diagram of a layer structure according to an embodiment of the invention is shown in the drawing. The figures are not drawn to scale, with certain ...

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Abstract

The invention provides a VDMOS structure inhibiting a parasitic transistor from opening and a manufacture method of the VDMOS structure. The VDMOS structure comprises a substrate, an epitaxial layer, a source doped region, a well region, a gate medium layer, a polysilicon grid, an insulation medium layer, a metal drain electrode and a metal source electrode, wherein the epitaxial layer covers the substrate, the source doped region is placed in the epitaxial layer, the well region is placed in the epitaxial layer and surrounds the source doped region, the gate medium layer is arranged between the surface of a channel region and the well region in a covered manner, the polysilicon grid covers the gate medium layer, the insulation medium layer is placed on the polysilicon grid, the edge of the insulation medium layer is connected with the gate medium layer, the metal drain electrode is paced under the substrate, the metal source electrode is placed at the surface of the epitaxial layer, and the metal source electrode penetrates the source doped region to reduce the length of the source doped region. The VDMOS structure can effectively inhibit the parasitic transistor from opening, and is higher in reliability.

Description

technical field [0001] The invention relates to the field of semiconductors, in particular to a VDMOS structure and a manufacturing method thereof that suppress parasitic transistors from being turned on. Background technique [0002] In the field of power semiconductors, a vertical metal-oxide-semiconductor-field-effect transistor (MOSFET) formed by a double-diffusion process is called a vertical double-diffusion insulated gate field-effect transistor (VDMOSFET, VDMOS for short). VDMOS has the characteristics of fast switching speed, high input impedance, high transconductance linearity, and negative temperature coefficient, so it has been widely used in switching power supply, DC-DC conversion, inverter, fast switching conversion and other fields. But in the above application, when the rate of change of the drain voltage is high, the parasitic transistor in the VDMOS will be turned on, thereby degrading its switching characteristics and safe operating area. For example, t...

Claims

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Application Information

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IPC IPC(8): H01L29/78H01L29/417H01L29/06H01L21/336H01L21/28
Inventor 邓海涛王立新王路璐李洵渠志光高博
Owner BEIJING ZHONGKE XINWEITE SCI & TECH DEV
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