Manufacturing method of 3D flash memory channel

Abstract

The present invention provides a method for manufacturing a 3D flash memory channel. First, the second channel dielectric layer and the first channel dielectric layer are etched, and then a second channel silicon is formed to cover the first channel dielectric layer. layer, to protect the first channel dielectric layer during subsequent etching, to avoid problems such as performance degradation caused by over-etching of the first channel dielectric layer caused by subsequent etching, and compared with the prior art, it can also reduce The use of the etching mask increases the process window of the double-pattern etching, which is beneficial to mass production.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a method for manufacturing a 3D flash memory channel. Background technique [0002] With the development of planar flash memory, the production process of semiconductors has made great progress. However, in recent years, the development of planar flash memory has encountered various challenges: physical limits, existing development technology limits, and storage electron density limits. In this context, various three-dimensional (3D) flash memory structures have emerged, such as 3D NAND flash memory, in order to solve the difficulties encountered by planar flash memory and to minimize the production cost per unit of memory cell. [0003] The channels and through-hole connections of the 3D NAND flash memory are formed by deep vias, and both are opened by overlay exposure to form deep vias. However, when deep vias are formed by the above method, there is usually an expo...

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Problems solved by technology

However, when the deep via hole is formed by the above method, there is usually an exposure offset, which will damage the dielectric layer at the corner of the top selection transistor when etching the via hole, so that the Vt control of the formed flash memory is unstable and the performance is degraded.

[0004] Specifically, please refer to figure 1 , figure 1 It is a schematic cross-sectional view of forming a channel for 3D flash memory in the prior art, including channel silicon 10 and dielectric layers on both sides of the channel silicon 10, and the dielectric layer is a thin film combination of silicon oxide-silicon nitride-silicon oxide (ONO ), that is, including the first silicon oxide 21, the second silicon nitride 22 and the third silicon oxide 23, the channel is formed in the insulating layer 30, after subsequent coating of photoresist and exposure to form a patterned photoresist 40, Due to process errors, the CD shifts and the dielectric layer in the channel is exposed. When etching, the dielectric layer will be over-etched, which will cause the above problems.

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