Resistor-capacitor reinforcement based memory cell of static random access memory
A storage unit, static random technology, applied in the field of integrated circuit design and manufacture, static random access memory, can solve problems such as excessive area and large number of transistors, achieve small area overhead, compatible with general technology, anti-single event flip Excellent performance
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Embodiment 1
[0024] Such as Figure 6 As shown, the storage unit of the RC-hardened static random access memory in this embodiment includes a latch circuit and a bit selection circuit, and the latch circuit consists of two PMOS transistors P1 and P2, two NMOS transistors N1 and N2, and a second NMOS transistor N1 and N2. A resistance-capacitance network and a second resistance-capacitance network; the bit selection circuit is composed of NMOS transistors N5 and N6; the latch circuit forms four storage points X1, X1B, X2, and X2B, which are set between complementary data storage points X1 and X1B Coupling capacitance C;
[0025] The drain of P1 is connected to X1, its source is connected to the power supply, and its gate is connected to X1B; the input and output terminals of the first resistance-capacitance network are respectively connected to X1 and X2; the drain of N1 is connected to X2, its source is grounded, and its Gate connection X2B;
[0026] The drain of P2 is connected to X1B, ...
Embodiment 2
[0031] The difference between this embodiment and the first embodiment is that the circuit design of the first RC network and the second RC network are different, and the position of the coupling capacitor C is different, and other parts are the same as the first embodiment.
[0032] Such as Figure 7As shown, the first RC network is composed of PMOS transistor P3 and NMOS transistor N3 that are always turned on to serve as the RC isolation point, and the second RC network is composed of PMOS transistor P4 that is always turned on to serve as the RC isolation point It is composed of N4 and NMOS tube; P3, P4, N3, and N4, which are always on, store redundant storage node information, forming six storage points X1, X1B, X2, X2B, X3, and X3B, and the complementary data storage points X3 and X3B A coupling capacitor C is set between them.
[0033] The source of P3 is connected to X1, its drain is connected to X3, its gate is grounded, and its substrate is connected to the power su...
Embodiment 3
[0040] The difference between this embodiment and the second embodiment is that the storage point connected to the bit selection circuit is different, and other parts are the same as the second embodiment.
[0041] Such as Figure 8 As shown, the drain of N5 is connected to X2, and the drain of N6 is correspondingly connected to X2B; the source of N5 is connected to the bit line BL; the source of N6 is connected to the complementary bit line BLB; the gates of N5 and N6 are connected together and connected to the word line on WL.
[0042] Embodiment three
[0043] The difference between this embodiment and the second embodiment is that the storage point connected to the bit selection circuit is different, and other parts are the same as the second embodiment.
[0044] Such as Figure 8 As shown, the drain of N5 is connected to X1, and the drain of N6 is connected to X1B; the source of N5 is connected to the bit line BL; the source of N6 is connected to the complementary bit ...
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