Successive approximation type analog-to-digital converter

Abstract

The invention provides a single-channel high-speed successive approximation type analog-to-digital converter reducing digital logic delay based on comparator logic. The successive approximation type analog-to-digital converter utilizes a switch control logic and lowest order half reference level comparison technology to lower a unit capacitor number needed by a traditional SAR ADC from 2N to (2N-2), and furthermore the power consumption and the chip area of the SAR ADC can be reduced. In addition, comparator control logic is employed to reduce digital delay on a feedback loop, therefore the conversion rate of the SARADC is raised, and an extra imbalance voltage correction circuit is avoided. The successive approximation type analog-to-digital converter can be applied in a sensor signal detection and data communication system, and has advantages of simple structure, small power consumption, small area, high integrated level and the like.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to a successive approximation analog-to-digital converter with reduced delay based on comparator logic. Background technique [0002] With the rapid development of science and technology in modern society, people's demand for digital technology is getting higher and higher. Smaller area, lower power consumption and higher integration have become the goals that modern people generally pursue for digital signal processing systems. With the continuous improvement of the process node of the integrated circuit, these goals are gradually realized in the digital signal processing chip of the integrated circuit. Among them, the Xeon series processors proposed by Intel at the 2015 ISSCC (International Solid-State Circuits Conference) conference adopt 22nm CMOS technology, the operating frequency can reach 3.8GHz, and the area is only 31.9mm×20.8mm. 5.56 billion tubes are integr...

AI Technical Summary

Problems solved by technology

[0005] This traditional successive approximation analog-to-digital converter has the following technical defects: (1) the traditional switch control logic requires a large number of unit capacitors, resulting in large power consumption and chip area; (2) due to process errors and failures Due to the existence of matching factors, multiple quantizer structures will require additional correction circuits or correct clock phases due to the difference in offset voltage between quantizers, thereby increasing the power consumption of the system or reducing the conversion rate of the system; (3) Plate sampling reduces overall converter slew rate due to extra charge redistribution phase

However, since each capacitor needs to introduce a corresponding V cm interface, which in turn requires more switches, and because V cm need to drive large capacitive loads which will make V cm The potential power consumption of the drive circuit is large

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