FinFET manufacturing method

A manufacturing method and technology of fins, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve the problems of increased impurity concentration and distribution widening, and achieve the effect of improving device performance and optimizing process

Active Publication Date: 2015-11-25
INST OF MICROELECTRONICS CHINESE ACAD OF SCI
View PDF4 Cites 14 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, in the process of forming PTSL by side scattering, the doping concentration at the bottom of the channel, that is, the surface of the isolation layer, is always the smallest, and the peak of the impurity distribution is often far away from t

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • FinFET manufacturing method
  • FinFET manufacturing method
  • FinFET manufacturing method

Examples

Experimental program
Comparison scheme
Effect test

Example Embodiment

[0019] In view of the above-mentioned problems, the present invention provides a FinFET manufacturing method, which effectively optimizes the PTSL distribution, so that it is well concentrated on the place where the punch-through current is generated, and at the same time does not affect other performance of the device. Specifically, the method includes:

[0020] a. A substrate 100 is provided, and fins 200 are formed on the substrate;

[0021] b. An isolation layer 300 is formed on the substrate on both sides of the fin 200;

[0022] c. forming a through barrier layer 310 in a portion of the fin covered by the isolation layer 300, so that the peak position of the impurity concentration in the through barrier layer is lower than the surface of the isolation layer;

[0023] d etch the isolation layer 300 so that its surface is flush with the position of the impurity concentration peak of the through barrier layer 310;

[0024] e. Source and drain regions are respectively formed at both ...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

PUM

PropertyMeasurementUnit
Thicknessaaaaaaaaaa
Login to view more

Abstract

The invention provides a FinFET manufacturing method. The method comprises steps: a substrate is provided, and a fin is formed on the substrate; b, isolation layers are formed on the substrate at two sides of the fin; a punch-through blocking layer is formed in part of the fin covered by the isolation layers to enable the position where the impurity concentration peak is in the punch-through blocking layer is lower than the surface of the isolation layer; d, each isolation layer is etched to enable the surface of the isolation layer to be flush with the position where the impurity concentration peak of the punch-through blocking layer is; and e, source-drain areas are formed at two ends of the fin respectively, a gate structure is formed when crossing the middle part of the fin, and filling by an interlayer dielectric layer is carried out above the isolation layer. Through the method provided by the invention, PTSL distribution can be effectively optimized, and the device performance is improved.

Description

technical field [0001] The present invention relates to a method for manufacturing a semiconductor device, in particular to a method for manufacturing a FinFET. technical background [0002] As the size of the semiconductor device is scaled down, there arises a problem that the threshold voltage decreases with the decrease of the channel length, that is, a short channel effect is generated in the semiconductor device. To meet the challenges from semiconductor design and manufacturing, led to the development of Fin Field Effect Transistor, or FinFET. [0003] The channel punching effect is a phenomenon in which the source junction and the depletion region of the drain junction of the field effect transistor are connected. When the channel is pierced through, the potential barrier between the source and the drain is significantly reduced, and a large number of carriers are injected from the source to the channel, and drift through the space charge region between the source an...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

Application Information

Patent Timeline
no application Login to view more
IPC IPC(8): H01L21/336
CPCH01L29/66803
Inventor 张珂珂尹海洲刘云飞
Owner INST OF MICROELECTRONICS CHINESE ACAD OF SCI
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Try Eureka
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap