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FinFET manufacturing method

A manufacturing method and technology of fins, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve the problems of increased impurity concentration and distribution widening, and achieve the effect of improving device performance and optimizing process

Active Publication Date: 2015-11-25
INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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Problems solved by technology

However, in the process of forming PTSL by side scattering, the doping concentration at the bottom of the channel, that is, the surface of the isolation layer, is always the smallest, and the peak of the impurity distribution is often far away from the bottom of the channel; if the doping concentration at the surface of the isolation layer is increased, Doping concentration, then the overall impurity concentration will increase and the distribution will widen, which is undesirable for the device

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Embodiment Construction

[0019] In view of the above problems, the present invention provides a FinFET manufacturing method, which effectively optimizes the distribution of PTSL so that it can be well concentrated in the place where the through current is generated without affecting other performances of the device. Specifically, the method includes:

[0020] a. providing a substrate 100, and forming fins 200 on the substrate;

[0021] b. forming isolation layers 300 on the substrates on both sides of the fin 200;

[0022] c. forming a punch-through barrier layer 310 in part of the fins covered by the isolation layer 300, so that the position of the impurity concentration peak in the punch-through barrier layer is lower than the surface of the isolation layer;

[0023] d. Etching the isolation layer 300 so that its surface is flush with the position where the impurity concentration peak of the punch-through barrier layer 310 is located;

[0024] e. Forming source and drain regions at both ends of th...

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Abstract

The invention provides a FinFET manufacturing method. The method comprises steps: a substrate is provided, and a fin is formed on the substrate; b, isolation layers are formed on the substrate at two sides of the fin; a punch-through blocking layer is formed in part of the fin covered by the isolation layers to enable the position where the impurity concentration peak is in the punch-through blocking layer is lower than the surface of the isolation layer; d, each isolation layer is etched to enable the surface of the isolation layer to be flush with the position where the impurity concentration peak of the punch-through blocking layer is; and e, source-drain areas are formed at two ends of the fin respectively, a gate structure is formed when crossing the middle part of the fin, and filling by an interlayer dielectric layer is carried out above the isolation layer. Through the method provided by the invention, PTSL distribution can be effectively optimized, and the device performance is improved.

Description

technical field [0001] The present invention relates to a method for manufacturing a semiconductor device, in particular to a method for manufacturing a FinFET. technical background [0002] As the size of the semiconductor device is scaled down, there arises a problem that the threshold voltage decreases with the decrease of the channel length, that is, a short channel effect is generated in the semiconductor device. To meet the challenges from semiconductor design and manufacturing, led to the development of Fin Field Effect Transistor, or FinFET. [0003] The channel punching effect is a phenomenon in which the source junction and the depletion region of the drain junction of the field effect transistor are connected. When the channel is pierced through, the potential barrier between the source and the drain is significantly reduced, and a large number of carriers are injected from the source to the channel, and drift through the space charge region between the source an...

Claims

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Application Information

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IPC IPC(8): H01L21/336
CPCH01L29/66803
Inventor 张珂珂尹海洲刘云飞
Owner INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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