On-chip integrated transformer

Abstract

The invention discloses an on-chip integrated transformer, which comprises a circuit layer, a transformer layer and a shielding layer, wherein the transformer layer is stacked on the circuit layer; and the shielding layer is arranged between the transformer layer and the circuit layer and is used for shielding an electric field formed on the transformer layer. Through a stacked design, high chip integration of a system is achieved; through adding the shielding layer, interlayer crosstalk on the transformer layer can be shielded; and the signal and power transmission performance of the transformer layer is ensured.

Description

technical field [0001] The invention belongs to the technical field of integrated circuits, and in particular relates to an on-chip integrated transformer, in particular to an on-chip integrated transformer with a shielding layer in a radio frequency integrated circuit. Background technique [0002] In recent years, with the rapid development of CMOS technology, integration and miniaturization have become the development trend of radio frequency integrated circuits (RFIC). As an important on-chip passive device, silicon-on-chip transformers are widely used in RF integrated circuits to implement functions such as impedance matching, power combining, AC coupling, DC isolation, and bandwidth expansion. [0003] Usually, the transformer on the silicon substrate occupies a relatively large area in the chip. In order to achieve better integration of the circuit and reduce the chip area, the transformer on the silicon substrate and other components in the circuit can be designed in...

AI Technical Summary

Problems solved by technology

Although this integrated stacked design method effectively reduces the area of ​​a single integrated chip, as the operating frequency continues to increase, the parasitic coupling effect of the transformer on the silicon substrate and other devices between layers increases sharply, resulting in a significant crosstalk effect between layers. The performance of the transformer and the stability of the circuit are severely affected

[0004] For example, the application number is: CN201110064627.X "A Vertical Structure On-Chip Integrated Transformer" and the application number is: CN200910047729.3 "On-Chip Small Area Laminated Structure Transformer" Chinese invention patent, the design of the silicon substrate transformer adopts The stacked structure is established, but the circuit devices are not designed for stacked integration

And the application number is: CN200710180625.0 "Hybrid On-Chip Off-Chip Transformer and Radio Frequency Identification System" Chinese patent, although the on-chip transformer and the integrated circuit unit are stacked as a whole, but the crosstalk between the transformer and other devices between the layers is shielded No solution is proposed, the crosstalk between layers leads to reliability problems in the system

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