Integrated circuit packaging structure and packaging technology based on Flip-chip connection

Abstract

The invention provides an integrated circuit packaging structure and a packaging technology based on Flip-chip connection. The integrated circuit packaging structure comprises a chip, metal projections arranged on the chip, nickel-plated palladium gold layers, chamfered silvered layers and a plastic-sealed body. The chamfered silvered layers are mutually-independent silvered segments. The chip is provided with the metal projections. The metal projections, the chip, the nickel-plated palladium gold layers and the chamfered silvered layers are plastically sealed in the plastic-sealed body. The metal projections, the chip, the chamfered silvered layers and the nickel-plated palladium gold layers form a power supply and signal channels of a circuit. The invention also provides the packaging technology of the above structure; the sliding risk of the integrated circuit packaging structure in a die is substantially lowered after a framework is thinned after corrosion; in addition, the pressure of a plastic-sealing material is reduced, and the integrated circuit packaging structure and the packaging technology are applicable to integrated circuit packaging.

Description

technical field [0001] The invention belongs to the technical field of integrated circuit packaging, and in particular relates to an integrated circuit packaging structure and packaging technology based on Flip-chip connections. Background technique [0002] Integrated circuit flat no-lead packaging (QFN / DFN), in recent years, with communication equipment (such as base stations, switches), smart phones, portable devices (such as tablet computers), wearable devices (such as smart watches, smart glasses, Smart bracelets, etc.) are popularized and developed rapidly, and are especially suitable for the packaging of large-scale integrated circuits with electrical requirements such as high frequency, high bandwidth, low noise, high thermal conductivity, small volume, and high speed. Integrated circuit flat no-lead packaging (QFN / DFN) effectively utilizes the packaging space of the lead pins, thereby greatly improving the packaging efficiency. Due to the short leads, small size of...

AI Technical Summary

Problems solved by technology

Traditional integrated circuit flat no-lead packaging (QFN / DFN) mainly has the following shortcomings: first, the design and production cycle is long, and the cost is relatively high; second, the arrangement of bumps and the density of I / O are affected by the frame design and The frame manufacturing process is limited; the third is that after the frame is corroded and thinned, there is a risk of sliding in the mold, and the reliability of the package cannot be guaranteed; the fourth is that the thickness of traditional QFN / DFN products is still relatively large, which cannot meet the requirements of current portable devices. Demand for Small Volume, High Density Packaging

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