Semiconductor wafer, flattening method therefor, and packaging method

Abstract

The invention provides a semiconductor wafer, its leveling method and packaging method. Wherein, the flattening method of a semiconductor wafer includes: providing a semiconductor wafer, the semiconductor wafer includes a functional surface formed with several semiconductor chips and a back surface opposite to the functional surface, and the semiconductor wafer has warping deformation; Afterwards, a stress layer is formed on the back of the semiconductor wafer, and the stress layer exerts stress on the wafer, thereby reducing the absolute value of the height difference between the edge and the center of the wafer, that is, reducing the warpage of the semiconductor wafer The flatness of the semiconductor wafer can be improved to improve the packaging effect of the semiconductor wafer and the cutting effect of the semiconductor wafer, so as to improve the yield rate of each chip formed after cutting the semiconductor wafer.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a semiconductor wafer, a flattening method and a packaging method thereof. Background technique [0002] Wafer Level Package (WLP) is a new packaging technology that has developed rapidly in recent years. In wafer-level packaging technology, the wafer is used as the processing object, and all semiconductor devices are completed on the wafer, and many chips are packaged, aged and tested on the wafer at the same time, and then the wafer is cut to form a single device. [0003] Compared with the traditional single-chip packaging technology, the wafer-level packaging technology eliminates the lead potting step, minimizes the package size, and makes the package size closer to the chip size; in addition, because the chip packaging, aging and testing steps are all It is carried out on silicon wafers, so the cost expenditure can be reduced through mass production. Based on the a...

AI Technical Summary

Problems solved by technology

[0006] For example, in the packaging process, if the wafer has a large degree of warpage (the degree of warpage is characterized by the degree of curvature of the wafer, numerically defined as the maximum value between points on the surface of the wafer in the direction perpendicular to the surface of the wafer. The height difference of the wafer; the greater the warpage of the wafer, the worse the surface flatness of the wafer), which will increase the distance difference between the parts of the superimposed adjacent two wafers, and reduce the superimposed adjacent two wafers. The alignment accuracy and packaging strength between wafers affect the quality of chips formed after subsequent dicing of wafers

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