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3D NAND flash memory structure and manufacturing method therefor

A manufacturing method and technology of flash memory, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., to achieve the effect of avoiding threshold voltage drift and leakage and improving quality

Active Publication Date: 2016-07-27
GIGADEVICE SEMICON SHANGHAI INC +1
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0005] In view of this, the embodiment of the present invention provides a 3D NAND flash memory structure and its manufacturing method to solve the problem in the prior art that the selection tube includes an electron trapping layer

Method used

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  • 3D NAND flash memory structure and manufacturing method therefor
  • 3D NAND flash memory structure and manufacturing method therefor
  • 3D NAND flash memory structure and manufacturing method therefor

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Embodiment 1

[0039] Based on the above description, Embodiment 1 of the present invention provides the following solution.

[0040] figure 2 It is a schematic flow chart of the manufacturing method of the 3D NAND flash memory structure provided in the embodiment of the present invention, such as figure 2 As shown, the method may include the following steps:

[0041] Step 21: Provide a substrate, and sequentially form a gate oxide layer, a GSL polysilicon layer, a plurality of stacked oxide dielectric layers and sacrificial dielectric layers, an SSL polysilicon layer, and a protective oxide layer on the substrate, wherein the sacrificial dielectric layer layers are formed between adjacent oxide dielectric layers;

[0042] Step 22, etching to form a cylindrical channel exposing the substrate;

[0043] Step 23, sequentially forming a tunnel oxide layer, polysilicon and a polysilicon isolation dielectric layer in the cylindrical trench;

[0044] Step 24, etching to form a source trench e...

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Abstract

The invention relates to the technical field of semiconductor manufacturing, and especially relates to a 3D NAND flash memory structure and a manufacturing method therefor. The method comprises the steps: providing a substrate, and sequentially forming a grid oxidation layer, a source selectron polycrystalline silicon layer, a plurality of stacked oxidation dielectric layers and sacrificial dielectric layers, a drain selectron polycrystalline silicon layer, and a protection oxidation layer; carrying out etching and forming a cylindrical trench exposing the substrate; forming a tunneling oxidation layer, polycrystalline silicon and a polycrystalline silicon isolation dielectric layer in the cylindrical trench; carrying out etching and forming a source trench exposing the substrate, and forming a public source electrode; carrying out wet etching, and removing the sacrificial dielectric layers; sequentially forming an electron capture layer and a blocking oxidation layer on a side wall of the source trench and an inner wall of the oxidation dielectric layer; and forming a grid electrode on the surface of the oxidation dielectric layer. A selectron prepared through the method does not contain electron capture layer silicon nitride, thereby avoiding the threshold voltage drift and electric leakage of the selectron, and improving the quality of a storage device.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a 3D NAND flash memory structure and a manufacturing method of the 3D NAND flash memory structure. Background technique [0002] With the rapid development of flash memory, the three-dimensional (3D) flash memory structure has been developed rapidly, and 3D NAND flash memory has been widely used in semiconductor devices. [0003] In the manufacturing method of existing 3D NAND flash memory structure, the manufacturing process of the drain selection transistor (StringSelectLine, SSL) and the source electrode selection transistor (GroundSelectLine, GSL) is consistent with the manufacturing process of the memory cell, that is, the gate of the selection transistor is formed In the process of oxidation (GateOxide) layer, it is inevitable to introduce electron trapping layer (ChargeTrapLayer) silicon nitride SiN into the selection tube. The selection tube includes ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/8247H01L27/115H10B43/20H10B43/35H10B69/00
Inventor 熊涛刘钊许毅胜舒清明
Owner GIGADEVICE SEMICON SHANGHAI INC
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