Method and system for realizing ultra-high-speed digital quadrature down-conversion and decimation filtering in FPGA

Abstract

The invention discloses a method and a system for realizing ultrahigh-speed digital orthogonal down conversion and decimation filtering in an FPGA. The system comprises the components of a plurality of ADC sampling chips, a high-speed ADC data receiving module, an over-clock processing module, a global clock module, a local numerical control oscillator and a multichannel digital decimation filter. The designed working frequency of the traditional FPGA is hard to exceed 200MHz. According to the method and the system, a numerical control oscillator (NCO) and the digital decimation filter as core parts in orthogonal down conversion are improved; furthermore through reasonably restraining layout and wiring of the FPGA, highest sampling rate above 500Msps and output baseband data rate above 125MHz can be ensured on a common FPGA device. Furthermore the method and the device can support simultaneous parallel sampling of multiple paths of ADC data, thereby adapting with a multichannel data receiving occasion.

Description

technical field [0001] The invention relates to the field of digital communication and radar signal processing, in particular to a method and system for realizing ultra-high-speed digital quadrature down-conversion and extraction filtering in FPGA. Background technique [0002] FPGA is the English abbreviation of Field Programmable Gate Array (Field Programmable Gate Array), which contains a large number of programmable resources, including look-up tables LUTs, registers, memories, hardware multipliers, phase-locked loops, etc. The programmable resources inside the FPGA chip can work in parallel, so it has extremely powerful processing capabilities, and its computing capabilities can reach hundreds of times or even higher than that of traditional CPUs. It is precisely because of this that in many signal processing platforms, FPGA assumes the core functions of computing and scheduling, and its main development method relies on hardware description language (hereinafter referr...

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Problems solved by technology

[0004] The technical problem to be solved by the present invention is to provide a method and system for realizing ultra-high-speed digital quadrature down-conversion and decimation filtering in FPGA. The present invention solves the problem of using FPGA to receive ADC data and perform quadrature Difficult technical problems in the design of down-conversion

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