A Layout Method Applicable to Capacitance Test Structure with Low Capacitance Density

Abstract

The invention discloses a layout method suitable for a low-capacitance density capacitance test structure. The low-capacitance density capacitance test structure comprises a device and a metal gasket group located in an outer frame, wherein the device is put at the lower part of the metal gasket group in a layout plane in an overlapping manner; the device comprises a metal wire, an upper pole plate polysilicon gate as one capacitor, a lower pole plate active region as another capacitor, an oxide isolation layer located between an upper pole plate and a lower pole plate and through holes; the metal gasket group comprises first metal gaskets connected with the active region, second metal gaskets connected with the polysilicon gate and third metal gaskets; the third metal gaskets are only connected with test probes in a probe group in a test; potential is added to the second metal gaskets through the corresponding test probes in the probe group in the test to avoid introduction of stray capacitance due to connection of the second metal gaskets and the polysilicon gate; and inner metal layers of the third metal gaskets are removed to avoid introduction of the stray capacitance.

Description

technical field [0001] The invention relates to the field of integrated circuit manufacturing, in particular to a domain layout optimization method applied to a low capacitance density capacitance test structure. Background technique [0002] Due to the high operating voltage of the high-voltage platform, the thickness of the gate oxide of the device is thick (the thickness of the high-voltage gate oxide is ~1000Α; the thickness of the low-voltage gate oxide is ~80Α), and the accuracy of the electrical testing machine is limited. If you want to accurately test the high-voltage MOS capacitor, from the formula C=( εS) / (4πkd), a large area of ​​two polar plates is required. [0003] in: [0004] ε: dielectric permittivity of the medium (relative permittivity) [0005] δ: Absolute permittivity in vacuum = 8.86×F / m [0006] k: electrostatic force constant, k=8.9880×10, unit: Nm / C (Newton meter 2 / coulomb 2 ) [0007] π: 3.1415926... [0008] S: The area facing the polar pl...

AI Technical Summary

Problems solved by technology

[0010] However, for the high-voltage MOS gate oxide capacitance test structure, the area required for accurate testing is about 10 4 um 2

For this kind of low capacitance density MOS gate oxide capacitance test structure, if placed between the metal pads, the device will overlap with the pads, and parasitic capacitance will be generated between the pads and the device

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