Technological method of shield grid trench-type power MOS device

Abstract

The invention discloses a technological method of a shield grid trench-type power MOS device. The method comprises the following steps: step 1: performing trench etching on a silicon substrate, and forming a sacrificial oxide layer; step 2: depositing a liner oxide layer, depositing polycrystalline silicon, back-etching, and forming a bottom polycrystalline silicon in a trench; step 3: forming a polycrystalline silicon interlayer medium oxide film; step 4: growing a heat oxide layer on the surface of an entire silicon sheet; step 5: back-etching the heat oxide layer; step 6: forming a grid oxide layer; and step 7: depositing polycrystalline silicon, back-etching, and forming an upper layer of polycrystalline silicon in the trench. The heat oxide layer process is first carried out after the polycrystalline silicon interlayer medium oxide film process, so that corners of the upper surface of the bottom polycrystalline silicon are rounded, thus increasing an exposure area of a silicon substrate material, in the subsequent growth process of the grid oxide layer, the grid oxide layer grows better, the thickness of the film is better in uniformity, and points that are easy to puncture are reduced.

Description

technical field [0001] The invention relates to the field of semiconductor device manufacturing, in particular to a shielding gate trench type power MOS device process method. Background technique [0002] The shielded gate trench power MOS device is a power semiconductor device widely used at present. It is etched in a semiconductor material such as a silicon substrate to form a trench, and after depositing a dielectric layer, it is filled with polysilicon, and the polysilicon is in the trench. The middle is divided into upper and lower layers. The specific manufacturing process is to etch a trench on the silicon substrate first, then deposit a sacrificial oxide layer, then deposit a pad oxide layer, then fill the trench with polysilicon and etch back to form the first layer of polysilicon, and then deposit Accumulate polysilicon interlayer dielectric oxide film, make gate oxide layer, etc., the shielded gate trench power MOS device formed by this process leads to poor Vra...

AI Technical Summary

Problems solved by technology

The reason for the specific analysis is that in the shielded gate trench type power MOS device manufacturing process, when the trench gate oxide layer is oxidized after the polysilicon interlayer dielectric oxide film is completed, the position of the lower corner of the gate oxide layer (and figure 2 As shown) the oxidation of the dielectric oxide film adjacent to the polysilicon layer is hindered, resulting in insufficient film thickness, that is, the thickness of the insulating medium here is thinner than that of the film at other positions. For example, after actual measurement, the film thickness at the lower corner is 41 nanometers, while other areas The average film thickness of the trench gate is 54 nanometers, so the withstand voltage at the lower corner is low to form a breakdown point, and the trench gate has poor withstand voltage

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