Through-silicon-via forming method and chip with through-silicon-via

Abstract

The invention relates to a through-silicon-via forming method and a chip with a through-silicon-via. The through-silicon-via forming method includes the steps: S1 forming a through hole in a silicon wafer; S2 forming an insulating layer on the wall of the through hole; S3 forming a diffusion barrier layer on the insulating layer; S4 forming a seed crystal layer on the diffusion barrier layer; S5 forming a conductor layer on the seed crystal layer, wherein the step S3 includes injecting first materials into the lower portion of the surface of the insulating layer by ion injection to form a first ion injection layer, and the step S4 includes injecting second materials into the lower portion of the surface of the diffusion barrier layer by ion injection to form a second ion injection layer.

Description

technical field [0001] The present invention generally relates to a method for manufacturing a through silicon via (TSV) and a chip including the through silicon via, which can be widely used in the interconnection between chips and the packaging technology of stacked chips In order to form a 3D packaging structure. Background technique [0002] In recent years, computers, communications, automotive electronics, aerospace industry and other consumer products have put forward high requirements for microelectronic packaging, that is, smaller, thinner, lighter, high reliability, multi-function, low power consumption and low cost. This has prompted the emergence of higher-density three-dimensional stacked packaging technologies. Three-dimensional stacked packaging can be divided into stacking of packages and stacking of silicon wafers. Currently, the stacking technology of packages can be obtained by stacking thin small outline packages (TSOPs) or stacking chip-scale packages...

AI Technical Summary

Problems solved by technology

In the production process of the barrier layer / seed layer, when the existing sputtering technology manufactures through-silicon holes with small apertures and high aspect ratios, it is difficult to complete the complete film formation in the through-holes, resulting in the failure of subsequent electroplating

The aspect ratio of TSVs is usually greater than 7:1, even as high as 12:1~15:1. Conventional magnetron sputtering technology is difficult to deposit a continuous conductor layer on the sidewalls of TSVs with high aspect ratios. Equipment manufacturers To this end, the highly ionized metal plasma magnetron sputtering technology was developed

However, none of these sputtering techniques can change the problem of low energy and poor uniformity of the sputtered particles, resulting in frequent defects in the film layer and voids in the subsequent electroplating copper layer

In addition, the bonding between the barrier layer and the seed layer made by sputtering and the silicon wafer is not strong, so the conductor layer in the TSV is easy to fall off

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