Process method for adding ILD (Inter Layer Deposition) filling window of adjustable control gate poly

Abstract

A process method for adding an ILD (Inter Layer Deposition) filling window of an adjustable control gate poly comprises the steps of providing a substrate with a cell memory region and a peripheral region; depositing a first poly gate layer on a surface of the substrate; growing a silicon oxide blocking layer on a surface of the first poly gate layer; performing photoresist coating and developing on a surface of the silicon oxide blocking layer to expose the peripheral region, and only etching to remove the silicon oxide blocking layer on the peripheral region; depositing second poly gate layers on surfaces of the silicon oxide blocking layer of the cell memory region and the first poly gate layer of the peripheral region; performing photoresist coating and developing on a surface of the second poly gate layers to expose the cell memory region, and etching to only remove the second poly gate layer on the cell memory region; etching to remove the remaining silicon oxide blocking layer; and performing photoresist coating and developing on surfaces of poly gates of the cell memory region and the peripheral region, and forming a final dual-poly gate structure by dry etching.

Description

technical field [0001] The invention relates to the field of integrated circuit manufacturing, in particular to a process method for increasing an ILD filling window with an adjustable control gate. Background technique [0002] A floating gate type non-volatile memory (Non-volatile memory, referred to as NVM) is a common integrated circuit device, which includes a source, a drain, a gate and a floating gate (Floating Gate). Generally, a floating-gate nonvolatile memory structure can be formed using a classic stack-gate process. The polysilicon layer close to the tunnel oxide layer is used as a floating gate, the top polysilicon layer is used as a control gate poly, and the insulating layer between the two polysilicon layers is a silicon dioxide or ONO (Oxide-Nitride-Oxide) structure. The effect of isolating the floating gate area. [0003] Compared with volatile memory, due to the existence of floating gate, non-volatile memory can still maintain data information even whe...

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Problems solved by technology

[0011] At present, the peripheral device area and the control gate of the unit storage area of ​​the floating gate nonvolatile memory can be deposited in one step by furnace tube technology, and the thickness is generally about 2000 angstroms, while the unit storage area of ​​the floating gate nonvolatile memory device In addition to the control gate with the same thickness as the peripheral device area, there is also a floating gate structure with a thickness of about 1000 angstroms. As the size of NVM continues to decrease, the aspect ratio of the space trench in the cell storage area increases greatly. , in the ILD (interlayer Deposition) process, it is very easy to generate voids (void), and it becomes very difficult to completely fill the trenches in the cell storage area, which will seriously affect the reliability of the device

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