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A kind of dual metal floating gate memory and its preparation method

A bimetallic and memory technology, applied in semiconductor devices, electrical solid devices, electrical components, etc., can solve the problems of nano-particles and dielectric layer interface effects, low device performance, etc., to improve storage levels, enhance storage performance, reduce The effect of power consumption

Active Publication Date: 2019-01-15
SHENZHEN UNIV
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Problems solved by technology

[0005] In view of the above-mentioned deficiencies in the prior art, the object of the present invention is to provide a double-metal floating gate memory and its preparation method, aiming at solving the impact of the existing double-layer nanoparticle floating gate structure on the interface between the nanoparticle and the dielectric layer, Issues that result in lower device performance

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  • A kind of dual metal floating gate memory and its preparation method
  • A kind of dual metal floating gate memory and its preparation method
  • A kind of dual metal floating gate memory and its preparation method

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[0029] The present invention provides a dual-metal floating gate memory and its preparation method. In order to make the purpose, technical solution and effect of the present invention clearer and clearer, the present invention will be further described in detail below. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention.

[0030] figure 1 It is a schematic structural diagram of a preferred embodiment of a dual-metal floating gate memory of the present invention, as shown in the figure, it includes a substrate 1, a gate 2, a blocking dielectric layer 3, a nanoparticle layer 4, a tunneling Dielectric layer 5, semiconductor layer 6, and source-drain electrodes (i.e. source 7 and drain 8); wherein, the material of the nanoparticle layer 4 is bimetallic alloy nanoparticles, and the nanoparticle layer 4 is nanoparticle single Floor.

[0031] The memory properties of single-metal na...

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Abstract

A dual-metal floating gate memory and its preparation method of the present invention, comprising the steps of: sequentially including a substrate, a gate, a blocking dielectric layer, a nanoparticle layer, a tunneling dielectric layer, a semiconductor layer, and a source-drain electrode from bottom to top ; Wherein, the material of the nanoparticle layer is a bimetallic alloy nanoparticle, and the nanoparticle layer is a nanoparticle monolayer. By selecting the bimetallic alloy nanoparticles, the invention can realize the adjustment and control of the Fermi energy level of the nanoparticles, so as to realize the adjustable performance of the memory. In addition, the microcontact printing method is used to prepare the bimetallic alloy nanoparticle layer with a single-layer structure, which can effectively save materials, reduce loss, and greatly reduce the manufacturing cost of storage devices. In addition, the structure of the memory device of the present invention can realize high-density storage, maintain high-performance operation of the memory device, regulate the energy level of the floating gate to achieve long-term storage of data, and realize the reading and writing speed and memory time of the bimetallic nanoparticle memory device. balance.

Description

technical field [0001] The invention relates to the field of organic field effect transistors, in particular to a dual-metal floating gate memory and a preparation method thereof. Background technique [0002] Fast memory is a very important electronic device in the field of semiconductor electronics, and has broad application prospects in the fields of information industry and electronics industry. In today's information age, memory should not only have small size, ultra-high capacity and fast reading and writing speed, but also have the characteristics of low power consumption, low cost and high reliability. Although silicon memory widely used in the market has the characteristics of fast read and write, expensive manufacturing equipment, complex photolithography process and peripheral transistor drive circuit increase its product cost, and the limited area of ​​silicon wafer and two-dimensional process limit However, its storage capacity cannot meet the requirements of l...

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/28
CPCH10K19/10
Inventor 周晔闫岩韩素婷周黎
Owner SHENZHEN UNIV
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