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Formation method of semiconductor device

A semiconductor and device technology, applied in the field of semiconductor device formation, can solve the problems that the electrical performance and reliability of semiconductor devices need to be improved, and achieve the effect of high ability and small damage

Active Publication Date: 2017-03-08
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Abstract
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  • Application Information

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Problems solved by technology

[0004] However, the electrical performance and reliability of semiconductor devices formed in the prior art need to be improved

Method used

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  • Formation method of semiconductor device
  • Formation method of semiconductor device
  • Formation method of semiconductor device

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Embodiment Construction

[0035] It can be seen from the background art that the electrical performance of semiconductor devices formed in the prior art needs to be improved.

[0036] It has been found through research that during the first patterning process of the initial hard mask layer, the etching gas used for the first patterning reacts chemically with the material of the initial hard mask layer to form a reaction by-product, and the etching gas It will also chemically react with the material of the first photoresist layer to form reaction by-products. Some of the reaction by-products will be taken away from the etching chamber with the flow of etching gas, and some of the reaction by-products will be taken away from the etching chamber under the action of their own gravity. The drops are attached to the first patterned hard mask layer, so that polymer impurities are formed on the first patterned hard mask layer and on the polysilicon layer around the first patterned hard mask layer . Since the ...

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Abstract

The invention discloses a formation method of a semiconductor device. The formation method comprises steps of: providing a substrate, a grid membrane arranged on the surface of the substrate and an initial mask layer arranged on the surface of the grid membrane; forming a graphical photoresist layer on the initial mask layer; taking the graphical photoresist layer as a mask, and etching the initial mask layer to form multiple separated hard mask layers, wherein polymer impurities are formed on the hard mask layers and the surface of the gate membrane; using the ashing technology to remove the graphical photoresist layer, wherein the ashing technology comprises first ashing technology and second ashing technology which are carries out successively, the first ashing technology is suitable for removing of silicon ions in the polymer impurities and the second ashing technology is suitable for removing carbon ions in the polymer impurities; after the ashing technology is performed, carrying out wet-process cleaning processing on the hard mask layers and the grid membrane; taking the hard mask layers as masks and etching the grid membrane so as to form multiple separated grid electrodes on the substrate; and forming a source region and a drainage region in the substrate on two sides of the grid electrodes. In this way, the quality of the formed grid electrodes is improved.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a method for forming a semiconductor device. Background technique [0002] At present, in the manufacturing process of semiconductor devices, a P-type metal oxide semiconductor (PMOS, P type Metal Oxide Semiconductor) tube, an N-type metal oxide semiconductor (NMOS, N type Metal Oxide Semiconductor) tube, or a combination of a PMOS tube and an NMOS tube The formed Complementary Metal Oxide Semiconductor (CMOS, Complementary Metal Oxide Semiconductor) tube is the main device constituting the chip. [0003] As semiconductor process nodes continue to decrease, the feature size of gates of semiconductor devices continues to decrease. In order to meet the development trend of decreasing semiconductor process nodes, a method for forming a gate using a double patterning (Double Patterning) method is proposed, which mainly includes: step S1, providing a substrate and...

Claims

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Application Information

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IPC IPC(8): H01L21/336H01L21/28
CPCH01L29/66484H01L21/28008
Inventor 张海洋孟晓莹韩秋华
Owner SEMICON MFG INT (SHANGHAI) CORP
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