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Methods to improve die edge yield

A yield, edge-to-edge technology, used in electrical components, circuits, semiconductor/solid-state device manufacturing, etc.

Active Publication Date: 2019-07-23
CSMC TECH FAB2 CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] Based on this, it is necessary to provide a method to improve the yield of crystal edge to reduce the problem of abnormal defects caused by substrate damage

Method used

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  • Methods to improve die edge yield
  • Methods to improve die edge yield
  • Methods to improve die edge yield

Examples

Experimental program
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Effect test

Embodiment 1

[0025] S110, a wafer substrate 100 is provided.

[0026] The specific type of substrate to be selected can be determined according to product requirements, including the material, crystal orientation, and doping type of the substrate, which are not limited here. Silicon substrates are commonly used in this field.

[0027] S120, photolithography forming a first photoresist layer.

[0028] See also Figure 5 , Applying glue on the wafer substrate 100 to form a first photoresist layer 210, and performing edge washing of the active area (using an organic solvent to remove the photoresist residue on the edge of the wafer) and photolithography. In this embodiment, the edge washing dimension a1 in the direction from the edge 120 of the wafer substrate to the axis 110 of the wafer substrate is large enough so that the area where the photoresist is washed away at least extends from the edge of the wafer to the subsequent metal deposition Process deposition area 300.

[0029] S130, forming a ...

Embodiment 2

[0046] Embodiment 1 protects the substrate by forming an oxide layer under the unfilled contact holes 10, and embodiment 2 removes excess ILD so that no contact holes are formed outside the deposition area 300, thereby preventing the slurry from passing through the contact holes 10The hidden dangers of corrosion of the substrate.

[0047] Therefore, the main difference between the second embodiment and the first embodiment is that the edge washing dimension a2 in the direction from the edge 120 of the wafer substrate to the axis 110 of the wafer substrate is reasonably set in step S160, so that the photoresist is washed away. It extends at least from the edge of the wafer to the deposition area 300. In this way, in step S170, the excess interlayer dielectric 220 will be etched away, directly avoiding the generation of the contact hole 10 that is not filled with metal. Such as Figure 7 Shown.

[0048] Similar to the embodiment 1, after step S190, a step of forming a metal connec...

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Abstract

The invention relates to a method for improving yield of a wafer edge. The method comprises the following steps of providing a wafer substrate; performing gelatinizing on the wafer substrate to form a first photoresist layer, and carrying out edge-washing on an active region; forming a silicon oxide isolation structure in the position, not covered by the first photoresist layer, on the wafer substrate; forming the active region on the wafer substrate; forming interlayer dielectric on the active region; performing gelatinizing on the interlayer dielectric to form a second photoresist layer, and performing edge-washing on contact holes; etching the interlayer dielectric under the sheltering of the second photoresist layer to form the contact holes; filling the contact holes with metal through a deposition process; and performing planarization processing on the interlayer dielectric filled with the metal, wherein the edge-washing region in the step of edge-washing for the active region at least extends from the edge of the wafer to the edge of a deposition region. By setting the proper edge-washing region, the wafer edge yield can be improved without extra cost.

Description

Technical field [0001] The invention relates to the field of integrated circuit (IC) manufacturing, in particular to a method for improving the edge yield in the edge washing process. Background technique [0002] During the glue coating process of the wafer, the centrifugal force will cause the photoresist to accumulate on the edge of the wafer to form residual protrusions, which in turn leads to pollution in subsequent processes and reduces the edge yield. In order to remove the photoresist residue accumulated on the edge of the wafer, edge Bean Removal (EBR) is usually performed after the glue coating process to remove the photoresist residue on the edge of the wafer. [0003] The improvement of the crystal edge yield is very important for the 8-inch factory and the process below 0.18um. In the traditional edge washing process, in the subsequent contact hole metal grinding process, the grinding fluid will corrode the silicon liner through the contact hole that is not filled with...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/768
CPCH01L21/76831
Inventor 陈亚威顾费东
Owner CSMC TECH FAB2 CO LTD
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