Method and system for reverse parsing of GPU instruction

Abstract

The invention provides a method and system for reverse parsing of a GPU instruction and relates to the technical fields of GPU microarchitecture and compiler code generation and program optimization. The method includes the steps that the GPU instruction is compiled to generate a compiled file, disassembling is conducted on the compiled file to generate a disassembled file, and the disassembled file is expressed as instMap variables through an assembling parser, wherein the types of the instMap variables include operation codes, modification codes, the instruction, operands and corresponding operand types; the instMap variables are input to a decoding solver, the decoding solver judges the types of the instMap variables and finds corresponding codes according to the determined operation codes or the determined modification codes. According to the method and the system, on the basis of decoding the instruction codes, through the combination with a PTX document, a GPU assembler can be constructed, the decoding assisting function is provided for the GPU assembler, the efficiency of a GPU program is improved, and a series of micro benchmark test programs can be designed and standardized to detect the characteristic and parameter of a GPU microarchitecture.

Description

technical field [0001] The invention relates to the technical fields of GPU micro-architecture, compiler code generation technology and program optimization, in particular to a method and system for reversely analyzing GPU instructions. Background technique [0002] Over the years, GPU manufacturers only provide users with the upper-layer API encapsulated by the driver, and expose their internal principles and details as little as possible, such as the software architecture of the driver, the microarchitecture of the GPU, and the instruction set. This has caused the academic community to lag far behind the industry in the field of GPU architecture research, and has been stagnant for a long time. In the era when GPUs were only used for graphics acceleration, this conservative strategy did not become a prominent problem in practical applications, and even had certain Rationality: the original drawing API is strongly related to hardware implementation, the API is just a simple ...

AI Technical Summary

Problems solved by technology

[0003] Nvidia, a GPU manufacturer in a monopoly position, maintains the inertia of closed technology, does not provide assemblers, does not support the lowest-level assembly programming, and does not disclose hardware architecture features that can only be controlled at the assembly level. As a supplement, it provides low-level Although the interface PTX is an intermediate representation very close to assembly, the control ability of PTX to hardware is lower than that of assembly. For example, PTX cannot control register allocation, nor can it precisely control the scheduling behavior of instructions. With less control, developers can only hope for compiler optimizations to improve performance, however, "Daniel JBernstein, Hsieh-Chung Chen, Chen-Mou Cheng, Tanja Lange, Ruben Niederhagen, Peter Schwabe, and Bo-Yin Yang. Usable assembly language for gpus: a success story. IACR Cryptology ePrint Archive, 2012:137, 2012.” pointed out that the code generated by the compiler NVCC provided by Nvidia is not very efficient, such as register allocation, there are a lot of bank conflicts. In fact, the Nvidia released Many parallel algorithm libraries are based on the internal assembler, and then manually compiled and optimized to achieve ideal efficiency. The problem is that unlike the 3D graphics field, which only has a small number of rendering engine developers, the user base of GPGPU is extensive and diverse. However, Nvidia only manually compiles and optimizes a small number of algorithm libraries, and only provides official support for a small number of large customers. The rest of the large number of users cannot extract the maximum performance from expensive GPGPU hardware. This is a huge waste of computing resources. The bad thing is that Nvidia has not optimized many core algorithms that are widely used, such as single-precision floating-point matrix multiplication (singe-precision matrix multiplication), Nvidia's manual assembly optimization version for the mainstream Kepler architecture, and the efficiency only reaches the theoretical peak 74% is the performance comparison between third-party optimized single-precision floating-point multiplication and SGEMM in NVIDIA manufacturer's cuBLAS. The performance of third-party assembly optimization is higher than that of cuBLAS. These studies show that assembly optimization is very valuable for mining GPU performance.

[0004] Some researchers have made some scattered progress on GPU performance tuning and tools, such as the microbenchmark program "Zhang, Yao, and John D. Owens."A quantitative performance analysis model forGPU architectures."In 2011 IEEE 17th International Symposium on HighPerformance Computer Architecture, pp.382-393. IEEE, 2011." "Xinxin Mei, KaiyongZhao, Chengjian Liu, and Xiaowen Chu. Benchmarking the memory hierarchy of modern gpus. In Network and Parallel Computing, pages 144–156. Springer, 2014. "Henry Wong, Misel-Myrto Papadopoulou, Maryam Sadooghi-Alvandi, and Andreas Moshovos. Demystifying gpu microarchitecture through microbenchmarking. In Performance Analysis of Systems & Software (ISPASS), 2010 IEEE International Symposium on, pages 235–206. IEEE", 235–206. IEEE, and GPU assembly-level optimization, however, their work is only concentrated on a single level, and they have not proposed a general technology that can be continued on the next-generation architecture, such as instruction cracking methods and corresponding automation tools. In addition, GPU has not yet Public benchmarking programs at the assembly level, most of the benchmarking programs in use are based on CUDA, resulting in unreliable test results

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