Multi-epitaxial semiconductor device and manufacturing method thereof

A manufacturing method and semiconductor technology, applied in the fields of semiconductor/solid-state device manufacturing, semiconductor devices, electric solid-state devices, etc., can solve the problems of size reduction, cost increase, unfavorable cost savings, etc. The effect of competitiveness

Active Publication Date: 2017-07-14
UNIV OF ELECTRONIC SCI & TECH OF CHINA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, this method will add a mask, which will increase the cost, which is not conducive to the cost saving of mass production. How to make BCD devices adapt to the reduction of device size without adding additional versions is an important task.

Method used

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  • Multi-epitaxial semiconductor device and manufacturing method thereof
  • Multi-epitaxial semiconductor device and manufacturing method thereof
  • Multi-epitaxial semiconductor device and manufacturing method thereof

Examples

Experimental program
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Effect test

Embodiment 1

[0039] Figure 4 Shown is a schematic diagram of the structure of a multi-epitaxial semiconductor device of the present invention, its cellular structure includes a multi-epitaxial semiconductor device, its cellular structure includes a substrate 1, a first epitaxial layer 2, a second epitaxial layer 21, a first STI isolation 131, second STI isolation 132, third STI isolation 133, first P well 31, third P well 33, fourth P well 34, DMOS source P-type heavily doped region 310, third P-type heavily doped region Doped region 37, fourth P-type heavily doped region 38, fifth P-type heavily doped region 39, DMOS source N-type heavily doped region 4, DMOS drain N-type heavily doped region 41, second N-type heavily doped region Type heavily doped region 43, the third N type heavily doped region 44, the fourth N type heavily doped region 45, the fifth N type heavily doped region 46, the DMOS source electrode 5, the contact electrode of the first P well 31 51, DMOS gate electrode 6, PM...

Embodiment 2

[0053] Such as image 3 As shown, this embodiment is basically the same as Embodiment 1, and the main difference is that the multi-epitaxial semiconductor device also includes a P Type doped region 314 , the upper surface of which is tangent to the upper surface of the second epitaxial layer 21 .

[0054] The manufacturing method of the above-mentioned multi-epitaxial semiconductor device is basically the same as the manufacturing method in Embodiment 1, the difference is that: P-type impurity ion implantation is performed after the growth of the second epitaxial layer 21 to form a P-type doped region 314, so that its upper surface and The upper surface of the second epitaxial layer 21 is tangential.

Embodiment 3

[0056] Such as Figure 5 As shown, this embodiment is basically the same as Embodiment 2, the main difference is that the P-type doped region 314 arranged between the first P well 31 and the N-type heavily doped region 41 of the DMOS drain, on which The surface is not tangent to the upper surface of the second epitaxial layer 21 .

[0057] The manufacturing method of the above-mentioned multi-epitaxial semiconductor device is basically the same as the manufacturing method in Embodiment 1, the difference is that: P-type impurity ion implantation is performed before the growth of the second epitaxial layer 21 to form a P-type doped region 314, so that the upper surface is not Tangent to the upper surface of the second epitaxial layer 21 .

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Abstract

The invention provides a multi-epitaxial semiconductor device and a manufacturing method thereof. A cellular structure of the multi-epitaxial semiconductor device comprises a substrate, an epitaxial layer, an STI isolation part, a P trap, a P-type heavily doped zone, an N-type heavily doped zone, a DMOS source electrode, a contact electrode of the first P trap, a DMOS gate electrode, a PMOS gate electrode, an NMOS gate electrode, a source electrode, a drain electrode, a BJT base electrode, a BJT emitter electrode, and a BJT collector electrode. Mask plate in an Nwell zone in terms of a BCD process are reduced, so costs of products in batch production are reduced, and competitiveness of products is improved. The concentration of the epitaxial layer serving as the Nwell zone is increased, so the number of carriers is increased when a DMOS device is in an open state. In this way, specific on-resistance of a DMOS is further reduced, the loss of the device is reduced, and the performance of the device is improved.

Description

technical field [0001] The invention relates to the technical field of semiconductor power devices, in particular to a multi-epitaxial semiconductor device and a manufacturing method thereof. Background technique [0002] Power integrated circuits integrate high-voltage power devices, control circuits, peripheral interface circuits, and protection circuits on the same chip. As a bridge between the signal processing part and the execution part of the system, it has a very wide range of applications. Power integration technology is a means to realize power integrated circuits, which need to achieve high and low voltage compatibility, high performance, high efficiency and high reliability in a limited chip area. Before the mid-1980s, power integrated circuits were mainly manufactured by a bipolar process. However, with the continuous improvement of the functional requirements for the control part, the power consumption and area of ​​the integrated circuit became larger and larg...

Claims

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Application Information

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IPC IPC(8): H01L27/06H01L21/8249
CPCH01L21/8249H01L27/0623
Inventor 乔明詹珍雅王正康梁龙飞王睿迪张波
Owner UNIV OF ELECTRONIC SCI & TECH OF CHINA
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