Silicon-on-insulator (SOI) dual-port static random access memory unit and a fabrication method thereof
A memory cell, static random technology, used in static memory, digital memory information, semiconductor/solid-state device manufacturing, etc., can solve problems such as increased leakage, achieve the effect of simple manufacturing process, eliminating chip area, and suppressing floating body effect
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Embodiment 1
[0109] The present invention provides a SOI dual-port static random access memory unit, please refer to Figure 5 , shown as a schematic diagram of the circuit principle of the SOI dual-port SRAM unit, including:
[0110] The first inverter 201 is composed of a first PMOS transistor 2011 and a first NMOS transistor 2012;
[0111] The second inverter 202 is composed of a second PMOS transistor 2021 and a second NMOS transistor 2022;
[0112] The acquisition transistor 203 is composed of a third NMOS transistor 2031 and a fourth NMOS transistor 2032, a fifth NMOS transistor 2033 and a sixth NMOS transistor 2034; the source of the third NMOS transistor 2031 is connected to the first inverter The output end and the input end of the second inverter, the gate is connected to the write word line WL1 of the memory, and the drain is connected to the write bit line BL1 of the memory; the source of the fourth NMOS transistor 2032 is connected to the first The output end of the two inve...
Embodiment 2
[0127]This embodiment adopts basically the same technical solution as Embodiment 1, the difference is that in Embodiment 1, for the NMOS transistor used in the inverter, the first heavily doped P-type region 2042 surrounds the first The vertical ends and lateral outer ends of a heavily doped N-type region 2041, the bottom of the first heavily doped N-type region 2041 is still in contact with the BOX, and a little leakage may still occur. The same is true for the PMOS transistors used in the inverters. In this embodiment, for the NMOS transistor used in the inverter, the first heavily doped P-type region 2042 not only surrounds the vertical ends and lateral outer ends of the first heavily doped N-type region 2041, but also further surrounds The bottom of the first heavily doped N-type region 2041; for the PMOS transistor used by the inverter, the second heavily doped N-type region surrounds both vertical ends and lateral outer ends of the second heavily doped P-type region , a...
Embodiment 3
[0130] The present invention also provides a method for manufacturing an SOI dual-port SRAM unit, comprising the steps of:
[0131] Step S1 is first performed: provide an SOI substrate including a back substrate, an insulating buried layer, and a top layer of silicon in sequence from bottom to top, and form a shallow trench isolation structure in the top layer of silicon to define an active region.
[0132] As an example, such as Figure 15 As shown, six active regions 20a, 20b, 20c, 20d, 20e and 20f are defined, wherein these six active regions 20e, 20a, 20b, 20c, 20d and 20f are arranged in parallel in sequence, and each active region is surrounded by a The shallow trench is filled with an insulating material to form a shallow trench isolation structure. In this embodiment, the insulating material is silicon dioxide.
[0133] Then execute step S2: as Figure 16 As shown, an N well 30, a first P well 40a, and a second P well 40b are fabricated in the top layer silicon acco...
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