Circuit and method for testing cycle time of SRAM

Abstract

The invention provides a circuit and method for testing the cycle time of an SRAM. The circuit comprises an address cycle shift register, a data cycle shift register and a control cycle shift register connected to the SRAM; address signals, data signals and control signals for the next test can be directly generated by utilization of pre-configured initial values and subsequent input clock pulse signals in the various cycle shift registers; a complex algorithm and logic calculation are unnecessary; the circuit is simple in structure and rapid in test speed; the overall test time of a semiconductor integrated circuit can be greatly shortened; and simultaneously, because of design of the cycle shift registers, the problem of test fault due to the fact that a BIST circuit on the periphery of the SRAM is failed at first in the prior art can be avoided.

Description

technical field [0001] The invention relates to the technical field of SRAM testing, in particular to a circuit and method for testing SRAM cycle time. Background technique [0002] With the development of storage technology, various types of semiconductor memories have emerged, such as static random access memory (SRAM), dynamic random access memory (DRAM), erasable programmable read-only memory (EPROM), electrically erasable programmable Read memory (EEPROM) and flash memory (Flash), etc. Among them, SRAM does not use capacitors, but stores data based on bistable flip-flops. In the case of uninterrupted power supply, each storage unit can store data 0 or 1 stably, so there is no need to periodically charge capacitors. That is, the data stored in it can be saved. As long as there is continuous power supply, SRAM can maintain its storage state without any data update operation. Because it can operate normally without constant charging, the processing speed of SRAM is fast...

AI Technical Summary

Problems solved by technology

[0004] When the existing BIST circuit uses a state machine to select and configure the test vector (or test mode) algorithm, the logic structure is complex and the speed is slow, which cannot meet the requirements for the fast cycle time test of the SRAM, and it is easy to cause the peripheral circuit of the SRAM to fail. Failure, and for high-speed, small-size SRAM, the value of its real cycle time may not be tested due to the failure of peripheral circuits such as BIST circuits

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