Silicon carbide power device terminal and manufacturing method thereof

Abstract

The invention discloses a silicon carbide powder device terminal and a manufacturing method thereof. The silicon carbide power device terminal comprises a first heavily-doped or second heavily-doped SiC substrate, a first lightly-doped SiC epitaxial layer, a second heavily-doped main junction, a first doped stop ring and at least one second heavily-doped partial pressure groove, wherein the first lightly-doped SiC epitaxial layer grows on the first heavily-doped or second heavily-doped SiC substrate; the second heavily-doped main junction and the first doped stop ring are provided with groove structures, and formed on the top of the first lightly-doped SiC epitaxial layer; and the at least one second heavily-doped partial pressure groove is formed between the second heavily-doped main junction and the first doped stop ring.

Description

technical field [0001] The invention relates to the field of semiconductor power devices, in particular to a silicon carbide power device terminal and a manufacturing method thereof. Background technique [0002] The third-generation semiconductor material silicon carbide (SiC) has the advantages of large band gap, high critical breakdown field strength, high thermal conductivity and high electron saturation rate, and is very suitable for making high-voltage, high-temperature, high-frequency, high-power semiconductor devices. Silicon carbide power devices (SiC diodes, SiC MOSFETs, etc.), as a new generation of high-efficiency power electronic devices, have become the most important development direction of power electronics technology, and have important applications in new energy vehicles, rail transit, locomotive traction, smart grid and other fields Prospects and development, and an important condition for silicon carbide power devices to have high withstand voltage chara...

AI Technical Summary

Problems solved by technology

The existing terminal structure design is complex, and the terminal occupies a large total area of ​​the chip, which is not conducive to increasing the current, and is sensitive to surface charges, and is easily affected by interface instability and oxide layer charges, thereby affecting the distribution of the electric field on the surface of the device, thereby affecting the device. Breakdown Voltage and Reliability

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