Multi-chip stacked package structure and packaging method thereof

Abstract

The present invention relates to a multi-chip stacked package structure and a packaging method thereof. According to the multi-chip stacked package structure and the packaging method thereof, only oneconnection sheet is disposed on the source of an HS chip and the drain of an LS chip to achieve the electrical connection of the HS chip and the LS chip, the conduction loss and switching loss of thepackage structure are reduced, and the heat dissipation efficiency of the package structure is enhanced; an IC chip is connected with the connection sheet in an insulated manner, and therefore, the IC chip can be stacked above a plane where the HS chip and the LS chip are located, and therefore, the size of a packaged device can be effectively decreased; the bottom surfaces of a first chip carrying stage and a second chip carrying stage can be exposed outside a package body; optionally, a part of the surface of a portion of the connection sheet which is not connected with the IC chip is exposed outside the package body; optionally, a heat dissipation plate is connected onto the connection sheet, and a part of the surface of the heat dissipation plate is exposed outside the package body; and optionally, the heat dissipation plate is inserted into a gap reserved in the package body so as to contact with the connection sheet to facilitate heat dissipation.

Description

[0001] This case is a divisional application [0002] Title of the original invention: A multi-chip stacked packaging structure and its packaging method [0003] Original application number: 201310617032.1 [0004] Date of original filing: November 27, 2013 technical field [0005] The invention relates to the field of semiconductors, in particular to a multi-chip stacked package structure and a package method thereof. Background technique [0006] In a DC-DC (direct current-direct current) converter, there are usually two MOSFETs (metal oxide semiconductor field effect transistors) as switching switches, one is a high-side MOSFET (HS for short), and the other is a low-side MOSFET (LS for short). ). Among them, the gate G1 of HS and the gate G2 of LS are connected to a controller (abbreviated as IC); the drain D1 of HS is connected to the Vin terminal, the source S1 is connected to the drain D2 of LS, and the source S2 of LS is connected to Gnd terminal to form the DC-DC...

AI Technical Summary

Problems solved by technology

However, for a specific packaging structure, the above-mentioned high-end MOSFET chip, low-end MOSFET chip and controller chip can only be arranged in parallel on the same plane of the lead frame, so the volume after packaging is large; moreover, they are only connected by wires The corresponding pins of the chip (for example, between the source S1 of the HS and the drain D2 of the LS) will increase the resistance and thermal resistance, which will affect the performance of the finished device

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