Preparation method and structure of three-dimensional memory
A memory, three-dimensional technology, applied in the direction of electric solid devices, semiconductor devices, electrical components, etc., can solve the problems such as the increase of electrode resistance of the metal gate 17 and the thickness loss of the tungsten metal gate 17, and achieve the effect of increasing the thickness
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[0039] Example one
[0040] reference Figure 10-14 As shown, the first embodiment of the present invention proposes a method for preparing a three-dimensional memory, which is characterized by including the following steps:
[0041] Such as Picture 10 As shown, a substrate 20 is provided, and an array storage area 21 and a peripheral circuit area 22 of a three-dimensional memory are formed on the substrate 20;
[0042] The display storage area 21 includes a multilayer stack structure in which silicon oxide layers 23 and silicon nitride layers 24 are alternately formed on the substrate 20; the number of layers of the stack structure is greater than or equal to 48 layers, preferably 48 layers and 64 layers , 80 layers, 96 layers, 112 layers or 128 layers.
[0043] Forming a multi-layer stacked structure into a storage core area 25 and a step area 26;
[0044] Such as Picture 10 As shown, a plurality of through holes 27 are formed in the storage core area 25;
[0045] Such as Picture 1...
Example Embodiment
[0050] Example two
[0051] The second embodiment of the present invention proposes a method for preparing a three-dimensional memory, which is characterized by including the following steps:
[0052] Such as Picture 10 As shown, a substrate 20 is provided, and an array storage area 21 and a peripheral circuit area 22 of a three-dimensional memory are formed on the substrate 20;
[0053] The display storage area 21 includes a multilayer stack structure in which silicon oxide layers 23 and silicon nitride layers 24 are alternately formed on the substrate 20;
[0054] A multi-layer stack structure is formed into a storage core region 25 and a step region 26; a step region 26 is formed on at least one side of the multi-layer stack structure by a photolithography process so that a portion of the upper surface of each silicon nitride layer 24 is exposed to Step area 26;
[0055] Such as Picture 10 As shown, an insulating layer 36 with a flat surface is formed on the substrate 20 to cover ...
Example Embodiment
[0061] Example three
[0062] The third embodiment of the present invention proposes a method for preparing a three-dimensional memory. In this embodiment, different parts from the above embodiments will be described, and the same parts will not be repeated.
[0063] The forming of the contact hole 34 electrically connected to the peripheral circuit area 22 includes patterning, etching, and metal filling the insulating layer 36 on the peripheral circuit area 22 to form an electrical connection with the peripheral circuit area 22 A plurality of first contact holes 34.
[0064] The forming of the contact hole 35 electrically connected to the metal gate 33 includes patterning, etching, and metal filling the insulating layer 26 on the array storage area 21 to form each metal of the array storage area 21 The gate 33 is electrically connected to a plurality of second contact holes 35.
[0065] The metal material used for the metal filling is tungsten.
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