Source region structure and preparation method of a trench transistor
A trench type, transistor technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., to achieve the effect of improving withstand voltage and low on-resistance
- Summary
- Abstract
- Description
- Claims
- Application Information
AI Technical Summary
Problems solved by technology
Method used
Image
Examples
Embodiment 1
[0038] In a preferred embodiment, as figure 1 As shown, a source region structure of a trench transistor is proposed, which may include:
[0039] The substrate 10 includes a body layer 11 and an epitaxial layer 12 formed on the upper surface of the body layer 11, and the epitaxial layer 12 has a first doping type;
[0040] a drift layer 20 formed on the upper surface of the substrate 10, and the drift layer 20 has a second doping type;
[0041] The upper surface of the drift layer 20 is formed with a plurality of laterally spaced first trenches TR1, and the upper part of the drift layer 20 on both sides of the first trench TR1 is formed with a source 51;
[0042] an oxide layer 30 covering the sidewall and bottom of the first trench TR1;
[0043] The conductive layer 40 fills the first trench TR1 and has a first doping type;
[0044] The dielectric layer 60 covers the upper surface of the source electrode 51 and the upper surface of the conductive layer 40;
[0045] a meta...
Embodiment 2
[0054] In a preferred embodiment, a trench transistor device structure is also proposed, which may include the above source region structure, and may also include:
[0055] The terminal area structure is arranged around the source area structure.
[0056] In the above embodiments, preferably, the termination region structure includes a trench-type isolation ring, and the isolation ring is used to isolate the termination region structure from the source region structure.
Embodiment 3
[0058] In a preferred embodiment, as Figure 2-7 As shown, a method for preparing a source region structure of a trench transistor is also proposed, which may include:
[0059] Step S1, providing a substrate 10, the substrate 10 includes a bulk layer 11 and an epitaxial layer 12 formed on the upper surface of the bulk layer 11, and the epitaxial layer 12 has a first doping type;
[0060] Step S2, forming a drift layer 20 on the upper surface of the substrate 10, and the drift layer 20 has a second doping type;
[0061] Step S3, etching the upper surface of the drift layer 20 to form a plurality of laterally spaced first trenches TR1;
[0062] Step S4, preparing an oxide layer 30 to cover the sidewall and bottom of the first trench TR1;
[0063]Step S5, using a conductive material to fill the first trench TR1 covered with the oxide layer 30 to form a conductive layer 40, and the conductive layer 40 has a first doping type;
[0064] Step S6, using an ion implantation process ...
PUM
| Property | Measurement | Unit |
|---|---|---|
| thickness | aaaaa | aaaaa |
Abstract
Description
Claims
Application Information
Login to View More 


