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Source region structure and preparation method of a trench transistor

A trench type, transistor technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., to achieve the effect of improving withstand voltage and low on-resistance

Active Publication Date: 2020-04-24
上海芯导电子科技股份有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, in the field of low-voltage and low-power MOSFETs, reducing the on-resistance of the device may affect the normally-off state of the MOSFET device, and further reducing the on-resistance of the device is limited

Method used

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  • Source region structure and preparation method of a trench transistor
  • Source region structure and preparation method of a trench transistor
  • Source region structure and preparation method of a trench transistor

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0038] In a preferred embodiment, as figure 1 As shown, a source region structure of a trench transistor is proposed, which may include:

[0039] The substrate 10 includes a body layer 11 and an epitaxial layer 12 formed on the upper surface of the body layer 11, and the epitaxial layer 12 has a first doping type;

[0040] a drift layer 20 formed on the upper surface of the substrate 10, and the drift layer 20 has a second doping type;

[0041] The upper surface of the drift layer 20 is formed with a plurality of laterally spaced first trenches TR1, and the upper part of the drift layer 20 on both sides of the first trench TR1 is formed with a source 51;

[0042] an oxide layer 30 covering the sidewall and bottom of the first trench TR1;

[0043] The conductive layer 40 fills the first trench TR1 and has a first doping type;

[0044] The dielectric layer 60 covers the upper surface of the source electrode 51 and the upper surface of the conductive layer 40;

[0045] a meta...

Embodiment 2

[0054] In a preferred embodiment, a trench transistor device structure is also proposed, which may include the above source region structure, and may also include:

[0055] The terminal area structure is arranged around the source area structure.

[0056] In the above embodiments, preferably, the termination region structure includes a trench-type isolation ring, and the isolation ring is used to isolate the termination region structure from the source region structure.

Embodiment 3

[0058] In a preferred embodiment, as Figure 2-7 As shown, a method for preparing a source region structure of a trench transistor is also proposed, which may include:

[0059] Step S1, providing a substrate 10, the substrate 10 includes a bulk layer 11 and an epitaxial layer 12 formed on the upper surface of the bulk layer 11, and the epitaxial layer 12 has a first doping type;

[0060] Step S2, forming a drift layer 20 on the upper surface of the substrate 10, and the drift layer 20 has a second doping type;

[0061] Step S3, etching the upper surface of the drift layer 20 to form a plurality of laterally spaced first trenches TR1;

[0062] Step S4, preparing an oxide layer 30 to cover the sidewall and bottom of the first trench TR1;

[0063]Step S5, using a conductive material to fill the first trench TR1 covered with the oxide layer 30 to form a conductive layer 40, and the conductive layer 40 has a first doping type;

[0064] Step S6, using an ion implantation process ...

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Abstract

The invention relates to the technical field of semiconductors and especially relates to a source region structure of a groove-type transistor and a preparation method of the source region structure.The source region structure includes a substrate comprising a body layer and a first epitaxial layer formed on the upper surface of the body layer and having a first doping type; a drift layer formedon the surface of the substrate and having a second doping type, wherein the upper surface of the drift layer is provided with a plurality of first grooves spaced transversely and source electrodes are formed on the upper part of the drift layer on two sides of each first channel; an oxidization layer covering side walls and bottoms of the first grooves; a conducting layer; a dielectric layer therein provided with multiple contact holes connecting the drift layer and the metal layer; and a metal layer covering the upper surface of the dielectric layer. Accumulation regions can be formed on side walls of the grooves, so that low conductance resistance can be realized. Besides, a normally off state of a device can be kept without external structural layers. At the same time, the drift layeracts as a buffer, so that the peak value electric field at the bottom of grid electrodes when drain electrodes have high voltage can be reduced and voltage withstanding capability of the device is improved.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a source region structure of a trench transistor and a preparation method thereof. Background technique [0002] With the continuous research and development of VVMOS (vertical v-groove MOSFET vertical V-groove metal oxide semiconductor field effect transistor, referred to as VVMOS), the power MOSFET has developed rapidly, and it has become the mainstream power semiconductor switching device in the field of small and medium power applications. Power MOSFETs have been developing in the direction of structural optimization and structural innovation, pushing device performance to a higher voltage application range, lower on-resistance, higher frequency and higher reliability. [0003] Power MOSFETs are three-terminal semiconductor switches commonly used for power and load control in circuits. In the case of a certain package power, the smaller the on-resistance of the device...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/28H01L29/417
CPCH01L21/28H01L29/41725
Inventor 俞峥陈敏欧新华袁琼符志岗刘宗金
Owner 上海芯导电子科技股份有限公司