Cavity-down ball grid array plastic package preparation method

Abstract

The invention relates to a cavity-down ball grid array plastic package preparation method. The method comprises the following steps of slot body forming, chip paster processing, bonding, film pasting,sealing, cutting channel forming, film peeling, and reballing. According to the invention, an isolating film is pasted in a reballing welding plate region; a chip, a bonding wire, and a welding plateare sealed and packaged at the same side of an IC carrier board by means of moulding; and then a sealing material and the isolating film on the welding plate are removed. Therefore, the sealing density, consistency, and flatness and the bonding strength with the IC carrier board are improved; the water absorption property after sealing is reduced; the reliability of the integrated circuit is improved obviously; and the high reliability requirement of the customer is met. According to the preparation method, with several kinds of processes like the laser process, the plasma process or the mechanical processing process, the moulding region can be processed flexibly and the thickness can be controlled; the high plastic package die costs are reduced; the long-term development cycle of the dieis shortened; and the operating costs and the development cycle are reduced.

Description

technical field [0001] The invention relates to a method for preparing a ball grid array plastic package, in particular to a method for preparing a cavity-down ball grid array plastic package, and belongs to the technical field of integrated circuit packaging. Background technique [0002] The ball grid array plastic package (PBGA) packaging form is that the pins are arranged in a two-dimensional array on a plane of the IC substrate, and it is a main packaging form of high-density plastic packaging of integrated circuits. The cavity down ball grid array plastic package (cavity down PBGA) is one of the package forms of the ball grid array plastic package (PBGA). Compared with the different sides of the IC carrier board, the array pins can not only reduce the overall thickness of the integrated circuit, but also save the other side of the IC carrier board for other developments, such as mounting the chip on the heat sink. Then install cooling devices such as fans and fins on ...

AI Technical Summary

Problems solved by technology

The ball grid array plastic packaging form with the cavity down, the traditional process is to use the potting process to encapsulate the chip and the bonding wires, the density, consistency, flatness and bonding strength with the IC carrier of the traditional packaging process are weak, reducing The reliability of the integrated circuit cannot be met, and the high reliability requirements of customers cannot be met. At the same time, the expensive plastic packaging mold cost and the long mold development cycle during the small batch production test increase the operating cost and development cycle.

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