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Fin type field effect transistor and forming method thereof

A technology of fin field effect transistors and fins, which is applied in semiconductor devices, electrical components, circuits, etc., to achieve high drive current, improve short channel effects, and improve electrical performance

Active Publication Date: 2018-04-24
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0005] However, the performance of the fin field effect transistor formed by the prior art needs to be further improved

Method used

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  • Fin type field effect transistor and forming method thereof
  • Fin type field effect transistor and forming method thereof
  • Fin type field effect transistor and forming method thereof

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Experimental program
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Effect test

Embodiment Construction

[0032] According to the background technology, the electrical performance of the fin field effect transistor formed in the prior art needs to be improved.

[0033] refer to figure 1 , figure 1 It is a schematic cross-sectional structure diagram of a fin field effect transistor, figure 1 The left figure in the middle is a schematic diagram of the cross-sectional structure perpendicular to the direction of fin extension. figure 1 The figure on the right side of the middle is a schematic cross-sectional structure parallel to the extending direction of the fin. The fin field effect transistor includes: a substrate 10; a fin 11 protruding from the substrate 10; An isolation structure 13 on and covering a part of the side wall of the fin 11, the isolation structure 13 covers a part of the side wall of the fin 11, and the top of the isolation structure 13 is lower than the top of the fin 11; The gate structure 14 on the structure 13 and across the fin 11; the groove in the fin 11 ...

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Abstract

The invention discloses a fin type field effect transistor and a forming method thereof. The forming method comprises the steps of: providing a substrate and a fin part protruding from the substrate,wherein the width dimension of the fin part is gradually reduced in a direction perpendicular to the surface of the substrate and pointing from the bottom part to the top part of the fin part, and along a direction perpendicular to a fin part extension direction; forming a gate structure that crosses the fin part on the substrate, wherein the gate structure covers part of the top part and side walls of the fin part; etching partial thickness of the fin part on two sides of the gate structure, and forming grooves in the fin part on two sides of the gate structure, wherein the width dimension ofbottom part of each groove is smaller than that of the top part of the groove in the fin part extension direction; and forming a source-drain epitaxially doped layer filling up the groove, wherein the source-drain epitaxially doped layer is doped with P-type ions or N-type ions. The forming method overcomes the problem that the gate structure has poor control capability for a source region and achannel region corresponding to the bottom part of a drain region because the side wall surfaces of the fin part are inclined, and improves the electrical performance of the formed fin type field effect transistor.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a fin field effect transistor and a forming method thereof. Background technique [0002] With the continuous development of semiconductor process technology, the development trend of semiconductor process nodes following Moore's Law continues to decrease. In order to adapt to the reduction of process nodes, the channel length of MOSFET field effect transistors has to be continuously shortened. The shortening of the channel length has the advantages of increasing the die density of the chip and increasing the switching speed of the MOSFET field effect tube. [0003] However, as the channel length of the device is shortened, the distance between the source and the drain of the device is also shortened, so that the control ability of the gate to the channel becomes worse, and the gate voltage pinches off the channel. The difficulty is also increasing, making t...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/78H01L21/336
CPCH01L29/66795H01L29/7853H01L29/7848H01L21/823878H01L21/823814H01L21/324H01L21/823821H01L21/26513H01L27/0924
Inventor 李勇
Owner SEMICON MFG INT (SHANGHAI) CORP
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