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ONO etching method for SONOS memory

A memory and dry etching technology, which is applied in the manufacture of electric solid state devices, semiconductor devices, semiconductor/solid state devices, etc., can solve the problems of plasma damage of the gate oxide layer at the bottom of the step height of the wafer, etc.

Active Publication Date: 2018-05-29
SHANGHAI HUALI MICROELECTRONICS CORP
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0005] The purpose of the present invention is to provide an ONO etching method for SONOS memory, to solve the change of the wafer step height caused by the front-layer STI CMP process in the existing ONO stacking process for removing the peripheral area and the device area and the impact on the STI The problem of plasma damage to the bottom gate oxide layer when the ONO sidewalls on both sides are removed

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  • ONO etching method for SONOS memory
  • ONO etching method for SONOS memory
  • ONO etching method for SONOS memory

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Embodiment Construction

[0034] The specific implementation manner of the present invention will be described in more detail below with reference to schematic diagrams. Advantages and features of the present invention will be apparent from the following description and claims. It should be noted that all the drawings are in a very simplified form and use imprecise scales, and are only used to facilitate and clearly assist the purpose of illustrating the embodiments of the present invention.

[0035] As mentioned in the background art, the ONO etching of the SONOS memory is an essential step in the semiconductor manufacturing industry, but currently there are many problems in the ONO etching process of the SONOS memory.

[0036] The inventor has studied a manufacturing method of SONOS memory, please refer to Figure 1 to Figure 3 ,Such as figure 1 As shown, firstly a semiconductor substrate 100 is provided, the surface of the semiconductor 100 substrate has at least a gate region, a device region and...

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Abstract

The invention provides an ONO etching method for a SONOS memory. A barrier layer is deposited on a substrate on which an ONO stack has been formed, the ONO side wall on both sides of the shallow trench isolation can be easily removed by utilizing isotropic characteristics of a wet etching process, without any plasma damage to a gate oxide layer at the bottom, and the device reliability is ensured.At the same time, the change in the wafer step height caused by the front shallow trench isolation and planarization polishing process can also be overcome, so that an etching window is greatly increased. The etching process is stable and controllable and suitable for mass production.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to an ONO etching method for a SONOS memory. Background technique [0002] With the continuous improvement of market requirements for the integration of FLASH storage devices, the contradictions between the reliability of data storage of traditional FLASH devices and the working speed, power consumption, and size of devices have become increasingly prominent. SONOS memory has the characteristics of small cell size, low operating voltage, and compatibility with CMOS technology. The continuous improvement of SONOS technology will promote the development of semiconductor memory in the direction of miniaturization, high performance, large capacity, and low cost. [0003] SONOS (Silicon-Oxide-Nitride-Oxide-Silicon, SONOS) memory replaces the floating gate structure in traditional FLASH memory devices with a base-tunnel oxide layer-silicon nitride-oxide layer-polysilicon gate st...

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Application Information

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IPC IPC(8): H01L21/311H01L27/11568
CPCH01L21/31111H01L21/31116H10B43/30
Inventor 刘政红辻直樹陈广龙黄冠群
Owner SHANGHAI HUALI MICROELECTRONICS CORP