Display panel, manufacturing method thereof and display device
A technology for a display panel and a manufacturing method, applied in the field of display panels and display devices, capable of solving problems such as planarization layer damage and poor display performance, achieving the effects of uniform thickness, avoiding poor display performance, and optimizing process methods
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Embodiment 1
[0041] The embodiment of the present application provides a method for manufacturing a display panel, the flow chart of the method is as follows figure 2 As shown, the method is used to solve the problem that the planarization layer is damaged during the anode etching process, resulting in poor display performance. The aforementioned poor display performance is mainly due to the fact that the planarization layer is damaged during the anode etching process, so that the overall thickness of the pixel definition layer formed on the planarization layer is uneven. Subsequently, in the process of evaporating the light-emitting layer, there is a gap between the mask plate and the pixel definition layer covered by the mask plate, so that the light-emitting layer is also evaporated in the pixel definition layer at the position covered by the mask plate, resulting in inaccurate evaporation positions of the light-emitting layer. Affects the luminous effect of the emissive layer. The me...
Embodiment 2
[0052] Based on the above-mentioned embodiments, this embodiment provides a better method for manufacturing a display panel. The process of the method is as follows: image 3 shown, including the following steps:
[0053] Step 31: Using a deposition process, forming an inorganic silicon compound film layer covering the via holes on the planarization layer;
[0054] Specifically, the material of the inorganic silicon compound film layer can be silicon oxide or silicon nitride, and the film layer can be deposited on the planarization layer by means of low-temperature chemical vapor deposition, which can cover the planarization layer and the transition layer in the planarization layer. hole location.
[0055] Step 32: Etching the inorganic silicon compound film layer at the position of the via hole to form an etching stopper layer having a first pattern.
[0056] Since the inorganic silicon compound film layer does not have good electrical conductivity and covers the via hole p...
Embodiment 3
[0065] Based on the above-mentioned embodiments, this embodiment provides another preferred method for manufacturing a display panel. The flow of the method is as follows: Figure 4 shown, including the following steps:
[0066] Step 41: Using a deposition process, forming a metal film layer covering the via holes on the planarization layer as an etching stopper layer.
[0067] Specifically, the material of the metal film layer may be an inert metal such as titanium or molybdenum, and the film layer may be deposited on the planarization layer by physical vapor deposition, which can cover the planarization layer and the positions of via holes in the planarization layer.
[0068] Since the metal film layer has a certain conductivity, the metal film layer covering the via hole will not significantly affect the signal transmission between the transmission line under the planarization layer and the anode layer. Therefore, there is no need to modify the position of the via hole The...
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Abstract
Description
Claims
Application Information
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