3d NAND detection structure and its formation method
A detection structure and stack structure technology, applied in semiconductor/solid-state device testing/measurement, electrical components, circuits, etc., can solve the problem of slow 3DNAND detection process, shorten the performance detection cycle, save costs, and simplify the process steps.
Active Publication Date: 2019-03-29
YANGTZE MEMORY TECH CO LTD
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Problems solved by technology
[0004] The existing 3D NAND detection process is slow, so it is necessary to design a 3D NAND detection structure to achieve fast detection
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[0022] The specific implementation of a 3D NAND detection structure and its forming method provided by the present invention will be described in detail below with reference to the accompanying drawings.
[0023] Please refer to figure 1 , is a structural schematic diagram of a 3D NAND detection structure.
[0024] For the above three stages of the read detection process, no matter which method is used, the well region (①), the control gate and / or step region conductive contact (②), the channel via structure (③) and the array The common source structure (④) is connected to the test terminal through a metal interconnection structure.
[0025] In the prior art, after the storage structure is completely formed, all electrical channels in the back-end process, including: well region (①), control gate and / or conductive contact (②), channel via structure ( ③) and the array common source structure (④) are all formed before testing can be carried out, and metal interconnection lines...
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The present invention relates to a 3D NAND test structure and a forming method thereof. The forming method comprises the following steps of providing a semiconductor substrate having a stacked structure dielectric layer formed on the surface of the semiconductor substrate, wherein the stacked structure is formed by stacking a sacrificial layer and an isolation layer and comprises a core a region and a stepped region surrounding the core region, and the dielectric layer covers the stacked structure; forming a common source trench penetrating the core region to the surface of the semiconductor substrate; removing the sacrificial layer along the common source trench, and forming an opening between the isolation layers; forming a control gate filling the opening and a conductive sidewall covering the sidewall of the common source trench and connected with the control gate. The 3D NAND test structure formed by the aforementioned method short-circuits all the control gates through the conductive sidewall on the sidewall of the common source trench, so that all the memory units can be tested only via a metal plug in connection with the control gate on the top layer.
Description
technical field [0001] The invention relates to the technical field of semiconductors, in particular to a 3D NAND detection structure and a forming method thereof. Background technique [0002] With the continuous development of 3D NAND technology, the storage structure of 3D NAND has exceeded 64 layers, and the parallel development of memory array chips and peripheral CMOS circuit chips will help to further improve development efficiency. Even memory array chips of different generations can share similar CMOS circuit chips to achieve higher storage capacity and memory cell density. [0003] In addition to basic research related to the process, how to quickly perform read testing is very important when the technology node reaches a higher generation. At present, the reading and testing process of 3D NAND memory is mainly divided into three stages: the first stage is to read the switching current of the memory cell through a semi-manual nanoprobe; the second stage is to pass...
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IPC IPC(8): H01L21/66
CPCH01L22/10H01L22/30
Inventor 肖莉红胡禺石孙坚华戴晓望张勇李思晢沈淼郭美澜汤召辉周玉婷
Owner YANGTZE MEMORY TECH CO LTD