Semiconductor structure and forming method thereof

Abstract

The invention relates to a semiconductor structure and a forming method thereof. The forming method of the semiconductor structure includes providing a substrate; forming a gate medium material layeron the surface of the substrate and a grid material layer disposed on the surface of the gate medium material layer; performing first ion doping on the grid material layer, wherein first doping ions adopted in the first ion doping can improve a segregation coefficient of P-type doping ions in the grid material layer; performing second ion doping on the grid material layer, wherein second doping ions adopted in second ion doping are P-type doping ions. By adopting the above semiconductor structure and the forming method thereof, grid depletion can be avoided and performance of the semiconductorstructure can be improved.

Description

Technical field [0001] The present invention relates to the field of semiconductor technology, in particular to a semiconductor structure and a method of forming the same. Background technique [0002] In the prior art, in PMOS devices, the gate is usually doped with P-type ion to adjust the work function between the gate of the transistor and the substrate, so as to achieve the purpose of adjusting the threshold voltage of the PMOS. In order to achieve electrical contact with the gate, a metal contact layer is formed on the top of the gate of the PMOS device. The metal contact layer is usually a metal silicide. [0003] In the process of 3D NAND, due to the large thermal budget, a relatively stable WSi is required 2 As the gate contact layer. P-type ion doping of the gate of PMOS devices is usually doped with B ion. However, B is doped in WSi 2 The middle segregation coefficient is high and the diffusion rate is fast, which causes B to pass through WSi 2 The interface between th...

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Problems solved by technology

The P-type ion doping of the gate of the PMOS device usually adopts B ion doping, however, B in WSi 2 The medium segregation coefficient is high and the diffusion rate is fast, causing B to cross the WSi 2 layer and gate interface, entering into the WSi 2 layer and in WSi 2 Accumulation in the layer, causing gate depletion, resulting in threshold voltage drift of PMOS devices, affecting the performance of PMOS transistors, so that it cannot meet the needs of high-speed and large-capacity circuits

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